src/dev/Pci.py

   1 # Copyright (c) 2013 ARM Limited
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   4 # The license below extends only to copyright in the software and shall
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  11 # modified or unmodified, in source code or in binary form.
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  13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
  14 # All rights reserved.
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  31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Nathan Binkert
  40
  41 from m5.SimObject import SimObject
  42 from m5.params import *
  43 from m5.proxy import *
  44 from Device import BasicPioDevice, DmaDevice, PioDevice
  45
  46 class PciConfigAll(BasicPioDevice):
  47     type = 'PciConfigAll'
  48     cxx_header = "dev/pciconfigall.hh"
  49     platform = Param.Platform(Parent.any, "Platform this device is part of.")
  50     bus = Param.UInt8(0x00, "PCI bus to act as config space for")
  51     size = Param.MemorySize32('16MB', "Size of config space")
  52
  53     pio_latency = '30ns'
  54     pio_addr = 0 # will be overridden by platform-based calculation
  55
  56
  57 class PciDevice(DmaDevice):
  58     type = 'PciDevice'
  59     cxx_class = 'PciDevice'
  60     cxx_header = "dev/pcidev.hh"
  61     abstract = True
  62     platform = Param.Platform(Parent.any, "Platform this device is part of.")
  63     config = SlavePort("PCI configuration space port")
  64     pci_bus = Param.Int("PCI bus")
  65     pci_dev = Param.Int("PCI device number")
  66     pci_func = Param.Int("PCI function code")
  67     pio_latency = Param.Latency('30ns', "Programmed IO latency")
  68     config_latency = Param.Latency('20ns', "Config read or write latency")
  69
  70     VendorID = Param.UInt16("Vendor ID")
  71     DeviceID = Param.UInt16("Device ID")
  72     Command = Param.UInt16(0, "Command")
  73     Status = Param.UInt16(0, "Status")
  74     Revision = Param.UInt8(0, "Device")
  75     ProgIF = Param.UInt8(0, "Programming Interface")
  76     SubClassCode = Param.UInt8(0, "Sub-Class Code")
  77     ClassCode = Param.UInt8(0, "Class Code")
  78     CacheLineSize = Param.UInt8(0, "System Cacheline Size")
  79     LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
  80     HeaderType = Param.UInt8(0, "PCI Header Type")
  81     BIST = Param.UInt8(0, "Built In Self Test")
  82
  83     BAR0 = Param.UInt32(0x00, "Base Address Register 0")
  84     BAR1 = Param.UInt32(0x00, "Base Address Register 1")
  85     BAR2 = Param.UInt32(0x00, "Base Address Register 2")
  86     BAR3 = Param.UInt32(0x00, "Base Address Register 3")
  87     BAR4 = Param.UInt32(0x00, "Base Address Register 4")
  88     BAR5 = Param.UInt32(0x00, "Base Address Register 5")
  89     BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
  90     BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
  91     BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
  92     BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
  93     BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
  94     BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
  95     BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO")
  96     BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO")
  97     BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO")
  98     BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
  99     BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
 100     BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
 101
 102     CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
 103     SubsystemID = Param.UInt16(0x00, "Subsystem ID")
 104     SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
 105     ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
 106     CapabilityPtr = Param.UInt8(0x00, "Capability List Pointer offset")
 107     InterruptLine = Param.UInt8(0x00, "Interrupt Line")
 108     InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
 109     MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
 110     MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
 111
 112     # Capabilities List structures for PCIe devices
 113     # PMCAP - PCI Power Management Capability
 114     PMCAPBaseOffset = \
 115         Param.UInt8(0x00, "Base offset of PMCAP in PCI Config space")
 116     PMCAPNextCapability = \
 117         Param.UInt8(0x00, "Pointer to next capability block")
 118     PMCAPCapId = \
 119         Param.UInt8(0x00, "Specifies this is the Power Management capability")
 120     PMCAPCapabilities = \
 121         Param.UInt16(0x0000, "PCI Power Management Capabilities Register")
 122     PMCAPCtrlStatus = \
 123         Param.UInt16(0x0000, "PCI Power Management Control and Status")
 124
 125     # MSICAP - Message Signaled Interrupt Capability
 126     MSICAPBaseOffset = \
 127         Param.UInt8(0x00, "Base offset of MSICAP in PCI Config space")
 128     MSICAPNextCapability = \
 129         Param.UInt8(0x00, "Pointer to next capability block")
 130     MSICAPCapId = Param.UInt8(0x00, "Specifies this is the MSI Capability")
 131     MSICAPMsgCtrl = Param.UInt16(0x0000, "MSI Message Control")
 132     MSICAPMsgAddr = Param.UInt32(0x00000000, "MSI Message Address")
 133     MSICAPMsgUpperAddr = Param.UInt32(0x00000000, "MSI Message Upper Address")
 134     MSICAPMsgData = Param.UInt16(0x0000, "MSI Message Data")
 135     MSICAPMaskBits = Param.UInt32(0x00000000, "MSI Interrupt Mask Bits")
 136     MSICAPPendingBits = Param.UInt32(0x00000000, "MSI Pending Bits")
 137
 138     # MSIXCAP - MSI-X Capability
 139     MSIXCAPBaseOffset = \
 140         Param.UInt8(0x00, "Base offset of MSIXCAP in PCI Config space")
 141     MSIXCAPNextCapability = \
 142         Param.UInt8(0x00, "Pointer to next capability block")
 143     MSIXCAPCapId = Param.UInt8(0x00, "Specifices this the MSI-X Capability")
 144     MSIXMsgCtrl = Param.UInt16(0x0000, "MSI-X Message Control")
 145     MSIXTableOffset = \
 146         Param.UInt32(0x00000000, "MSI-X Table Offset and Table BIR")
 147     MSIXPbaOffset = Param.UInt32(0x00000000, "MSI-X PBA Offset and PBA BIR")
 148
 149     # PXCAP - PCI Express Capability
 150     PXCAPBaseOffset = \
 151         Param.UInt8(0x00, "Base offset of PXCAP in PCI Config space")
 152     PXCAPNextCapability = Param.UInt8(0x00, "Pointer to next capability block")
 153     PXCAPCapId = Param.UInt8(0x00, "Specifies this is the PCIe Capability")
 154     PXCAPCapabilities = Param.UInt16(0x0000, "PCIe Capabilities")
 155     PXCAPDevCapabilities = Param.UInt32(0x00000000, "PCIe Device Capabilities")
 156     PXCAPDevCtrl = Param.UInt16(0x0000, "PCIe Device Control")
 157     PXCAPDevStatus = Param.UInt16(0x0000, "PCIe Device Status")
 158     PXCAPLinkCap = Param.UInt32(0x00000000, "PCIe Link Capabilities")
 159     PXCAPLinkCtrl = Param.UInt16(0x0000, "PCIe Link Control")
 160     PXCAPLinkStatus = Param.UInt16(0x0000, "PCIe Link Status")
 161     PXCAPDevCap2 = Param.UInt32(0x00000000, "PCIe Device Capabilities 2")
 162     PXCAPDevCtrl2 = Param.UInt32(0x00000000, "PCIe Device Control 2")