SCons: Support building without an ISA
[gem5.git] / src / dev / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2006 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Steve Reinhardt
30 # Gabe Black
31
32 Import('*')
33
34 if env['TARGET_ISA'] == 'no':
35 Return()
36
37 if env['FULL_SYSTEM']:
38 SimObject('BadDevice.py')
39 SimObject('CopyEngine.py')
40 SimObject('Device.py')
41 SimObject('DiskImage.py')
42 SimObject('Ethernet.py')
43 SimObject('Ide.py')
44 SimObject('Pci.py')
45 SimObject('Platform.py')
46 SimObject('SimpleDisk.py')
47 SimObject('Terminal.py')
48 SimObject('Uart.py')
49
50 Source('baddev.cc')
51 Source('copy_engine.cc')
52 Source('disk_image.cc')
53 Source('etherbus.cc')
54 Source('etherdevice.cc')
55 Source('etherdump.cc')
56 Source('etherint.cc')
57 Source('etherlink.cc')
58 Source('etherpkt.cc')
59 Source('ethertap.cc')
60 Source('i8254xGBe.cc')
61 Source('ide_ctrl.cc')
62 Source('ide_disk.cc')
63 Source('intel_8254_timer.cc')
64 Source('io_device.cc')
65 Source('isa_fake.cc')
66 Source('mc146818.cc')
67 Source('ns_gige.cc')
68 Source('pciconfigall.cc')
69 Source('pcidev.cc')
70 Source('pktfifo.cc')
71 Source('platform.cc')
72 Source('simple_disk.cc')
73 Source('sinic.cc')
74 Source('terminal.cc')
75 Source('uart.cc')
76 Source('uart8250.cc')
77
78 TraceFlag('DiskImageRead')
79 TraceFlag('DiskImageWrite')
80 TraceFlag('DMA')
81 TraceFlag('DMACopyEngine')
82 TraceFlag('Ethernet')
83 TraceFlag('EthernetCksum')
84 TraceFlag('EthernetDMA')
85 TraceFlag('EthernetData')
86 TraceFlag('EthernetDesc')
87 TraceFlag('EthernetEEPROM')
88 TraceFlag('EthernetIntr')
89 TraceFlag('EthernetPIO')
90 TraceFlag('EthernetSM')
91 TraceFlag('IdeCtrl')
92 TraceFlag('IdeDisk')
93 TraceFlag('Intel8254Timer')
94 TraceFlag('IsaFake')
95 TraceFlag('MC146818')
96 TraceFlag('PCIDEV')
97 TraceFlag('PciConfigAll')
98 TraceFlag('SimpleDisk')
99 TraceFlag('SimpleDiskData')
100 TraceFlag('Terminal')
101 TraceFlag('TerminalVerbose')
102 TraceFlag('Uart')
103
104 CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
105 CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
106 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
107 'EthernetCksum', 'EthernetEEPROM' ])
108 CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
109 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
110 CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
111