1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nathan Binkert
29 from m5
.params
import *
30 from m5
.proxy
import *
31 from BadDevice
import BadDevice
32 from AlphaBackdoor
import AlphaBackdoor
33 from Device
import BasicPioDevice
, IsaFake
, BadAddr
34 from Pci
import PciConfigAll
35 from Platform
import Platform
36 from Uart
import Uart8250
38 class TsunamiCChip(BasicPioDevice
):
40 cxx_header
= "dev/alpha/tsunami_cchip.hh"
41 tsunami
= Param
.Tsunami(Parent
.any
, "Tsunami")
43 class TsunamiIO(BasicPioDevice
):
45 cxx_header
= "dev/alpha/tsunami_io.hh"
46 time
= Param
.Time('01/01/2009',
47 "System time to use ('Now' for actual time)")
48 year_is_bcd
= Param
.Bool(False,
49 "The RTC should interpret the year as a BCD value")
50 tsunami
= Param
.Tsunami(Parent
.any
, "Tsunami")
51 frequency
= Param
.Frequency('1024Hz', "frequency of interrupts")
53 class TsunamiPChip(BasicPioDevice
):
55 cxx_header
= "dev/alpha/tsunami_pchip.hh"
56 tsunami
= Param
.Tsunami(Parent
.any
, "Tsunami")
58 class Tsunami(Platform
):
60 cxx_header
= "dev/alpha/tsunami.hh"
61 system
= Param
.System(Parent
.any
, "system")
63 cchip
= TsunamiCChip(pio_addr
=0x801a0000000)
64 pchip
= TsunamiPChip(pio_addr
=0x80180000000)
65 pciconfig
= PciConfigAll()
66 fake_sm_chip
= IsaFake(pio_addr
=0x801fc000370)
68 fake_uart1
= IsaFake(pio_addr
=0x801fc0002f8)
69 fake_uart2
= IsaFake(pio_addr
=0x801fc0003e8)
70 fake_uart3
= IsaFake(pio_addr
=0x801fc0002e8)
71 fake_uart4
= IsaFake(pio_addr
=0x801fc0003f0)
73 fake_ppc
= IsaFake(pio_addr
=0x801fc0003bb)
75 fake_OROM
= IsaFake(pio_addr
=0x800000a0000, pio_size
=0x60000)
77 fake_pnp_addr
= IsaFake(pio_addr
=0x801fc000279)
78 fake_pnp_write
= IsaFake(pio_addr
=0x801fc000a79)
79 fake_pnp_read0
= IsaFake(pio_addr
=0x801fc000203)
80 fake_pnp_read1
= IsaFake(pio_addr
=0x801fc000243)
81 fake_pnp_read2
= IsaFake(pio_addr
=0x801fc000283)
82 fake_pnp_read3
= IsaFake(pio_addr
=0x801fc0002c3)
83 fake_pnp_read4
= IsaFake(pio_addr
=0x801fc000303)
84 fake_pnp_read5
= IsaFake(pio_addr
=0x801fc000343)
85 fake_pnp_read6
= IsaFake(pio_addr
=0x801fc000383)
86 fake_pnp_read7
= IsaFake(pio_addr
=0x801fc0003c3)
88 fake_ata0
= IsaFake(pio_addr
=0x801fc0001f0)
89 fake_ata1
= IsaFake(pio_addr
=0x801fc000170)
91 fb
= BadDevice(pio_addr
=0x801fc0003d0, devicename
='FrameBuffer')
92 io
= TsunamiIO(pio_addr
=0x801fc000000)
93 uart
= Uart8250(pio_addr
=0x801fc0003f8)
94 backdoor
= AlphaBackdoor(pio_addr
=0x80200000000, disk
=Parent
.simple_disk
)
96 # Attach I/O devices to specified bus object. Can't do this
97 # earlier, since the bus object itself is typically defined at the
99 def attachIO(self
, bus
):
100 self
.cchip
.pio
= bus
.master
101 self
.pchip
.pio
= bus
.master
102 self
.pciconfig
.pio
= bus
.default
103 bus
.use_default_range
= True
104 self
.fake_sm_chip
.pio
= bus
.master
105 self
.fake_uart1
.pio
= bus
.master
106 self
.fake_uart2
.pio
= bus
.master
107 self
.fake_uart3
.pio
= bus
.master
108 self
.fake_uart4
.pio
= bus
.master
109 self
.fake_ppc
.pio
= bus
.master
110 self
.fake_OROM
.pio
= bus
.master
111 self
.fake_pnp_addr
.pio
= bus
.master
112 self
.fake_pnp_write
.pio
= bus
.master
113 self
.fake_pnp_read0
.pio
= bus
.master
114 self
.fake_pnp_read1
.pio
= bus
.master
115 self
.fake_pnp_read2
.pio
= bus
.master
116 self
.fake_pnp_read3
.pio
= bus
.master
117 self
.fake_pnp_read4
.pio
= bus
.master
118 self
.fake_pnp_read5
.pio
= bus
.master
119 self
.fake_pnp_read6
.pio
= bus
.master
120 self
.fake_pnp_read7
.pio
= bus
.master
121 self
.fake_ata0
.pio
= bus
.master
122 self
.fake_ata1
.pio
= bus
.master
123 self
.fb
.pio
= bus
.master
124 self
.io
.pio
= bus
.master
125 self
.uart
.pio
= bus
.master
126 self
.backdoor
.pio
= bus
.master