src/dev/alpha/tsunami.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /**
  32  * @file
  33  * Declaration of top level class for the Tsunami chipset. This class just
  34  * retains pointers to all its children so the children can communicate.
  35  */
  36
  37 #ifndef __DEV_TSUNAMI_HH__
  38 #define __DEV_TSUNAMI_HH__
  39
  40 #include "dev/platform.hh"
  41
  42 class IdeController;
  43 class TsunamiCChip;
  44 class TsunamiPChip;
  45 class TsunamiIO;
  46 class System;
  47
  48 /**
  49   * Top level class for Tsunami Chipset emulation.
  50   * This structure just contains pointers to all the
  51   * children so the children can commnicate to do the
  52   * read work
  53   */
  54
  55 class Tsunami : public Platform
  56 {
  57   public:
  58     /** Max number of CPUs in a Tsunami */
  59     static const int Max_CPUs = 64;
  60
  61     /** Pointer to the system */
  62     System *system;
  63
  64     /** Pointer to the TsunamiIO device which has the RTC */
  65     TsunamiIO *io;
  66
  67     /** Pointer to the Tsunami CChip.
  68      * The chip contains some configuration information and
  69      * all the interrupt mask and status registers
  70      */
  71     TsunamiCChip *cchip;
  72
  73     /** Pointer to the Tsunami PChip.
  74      * The pchip is the interface to the PCI bus, in our case
  75      * it does not have to do much.
  76      */
  77     TsunamiPChip *pchip;
  78
  79     int intr_sum_type[Tsunami::Max_CPUs];
  80     int ipi_pending[Tsunami::Max_CPUs];
  81
  82   public:
  83     /**
  84      * Constructor for the Tsunami Class.
  85      * @param name name of the object
  86      * @param s system the object belongs to
  87      * @param intctrl pointer to the interrupt controller
  88      */
  89     Tsunami(const std::string &name, System *s, IntrControl *intctrl);
  90
  91     /**
  92      * Return the interrupting frequency to AlphaAccess
  93      * @return frequency of RTC interrupts
  94      */
  95     virtual Tick intrFrequency();
  96
  97     /**
  98      * Cause the cpu to post a serial interrupt to the CPU.
  99      */
 100     virtual void postConsoleInt();
 101
 102     /**
 103      * Clear a posted CPU interrupt (id=55)
 104      */
 105     virtual void clearConsoleInt();
 106
 107     /**
 108      * Cause the chipset to post a cpi interrupt to the CPU.
 109      */
 110     virtual void postPciInt(int line);
 111
 112     /**
 113      * Clear a posted PCI->CPU interrupt
 114      */
 115     virtual void clearPciInt(int line);
 116
 117
 118     virtual Addr pciToDma(Addr pciAddr) const;
 119
 120     /**
 121      * Calculate the configuration address given a bus/dev/func.
 122      */
 123     virtual Addr calcConfigAddr(int bus, int dev, int func);
 124
 125     /**
 126      * Serialize this object to the given output stream.
 127      * @param os The stream to serialize to.
 128      */
 129     virtual void serialize(std::ostream &os);
 130
 131     /**
 132      * Reconstruct the state of this object from a checkpoint.
 133      * @param cp The checkpoint use.
 134      * @param section The section name of this object
 135      */
 136     virtual void unserialize(Checkpoint *cp, const std::string &section);
 137 };
 138
 139 #endif // __DEV_TSUNAMI_HH__