2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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33 * Emulation of the Tsunami CChip CSRs
40 #include "arch/alpha/ev5.hh"
41 #include "base/trace.hh"
42 #include "cpu/intr_control.hh"
43 #include "cpu/thread_context.hh"
44 #include "dev/alpha/tsunami.hh"
45 #include "dev/alpha/tsunami_cchip.hh"
46 #include "dev/alpha/tsunamireg.h"
47 #include "mem/packet.hh"
48 #include "mem/packet_access.hh"
49 #include "mem/port.hh"
50 #include "params/TsunamiCChip.hh"
51 #include "sim/system.hh"
54 //Should this be AlphaISA?
55 using namespace TheISA
;
57 TsunamiCChip::TsunamiCChip(const Params
*p
)
58 : BasicPioDevice(p
), tsunami(p
->tsunami
)
66 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
72 //Put back pointer in tsunami
73 tsunami
->cchip
= this;
77 TsunamiCChip::read(PacketPtr pkt
)
79 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
81 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
83 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
84 Addr daddr
= (pkt
->getAddr() - pioAddr
);
87 switch (pkt
->getSize()) {
89 case sizeof(uint64_t):
90 pkt
->set
<uint64_t>(0);
92 if (daddr
& TSDEV_CC_BDIMS
)
94 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
98 if (daddr
& TSDEV_CC_BDIRS
)
100 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
109 panic("TSDEV_CC_MTR not implemeted\n");
112 pkt
->set(((ipint
<< 8) & 0xF) | ((itint
<< 4) & 0xF) |
113 (pkt
->req
->contextId() & 0x3));
114 // currently, FS cannot handle MT so contextId and
115 // cpuId are effectively the same, don't know if it will
116 // matter if FS becomes MT enabled. I suspect no because
117 // we are currently able to boot up to 64 procs anyway
118 // which would render the CPUID of this register useless
155 panic("TSDEV_CC_PRBEN not implemented\n");
161 panic("TSDEV_CC_IICx not implemented\n");
167 panic("TSDEV_CC_MPRx not implemented\n");
176 panic("default in cchip read reached, accessing 0x%x\n");
180 case sizeof(uint32_t):
181 case sizeof(uint16_t):
182 case sizeof(uint8_t):
184 panic("invalid access size(?) for tsunami register!\n");
186 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
187 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
189 pkt
->makeAtomicResponse();
194 TsunamiCChip::write(PacketPtr pkt
)
196 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
197 Addr daddr
= pkt
->getAddr() - pioAddr
;
198 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
201 assert(pkt
->getSize() == sizeof(uint64_t));
203 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
205 bool supportedWrite
= false;
208 if (daddr
& TSDEV_CC_BDIMS
)
210 int number
= (daddr
>> 4) & 0x3F;
216 olddim
= dim
[number
];
217 olddir
= dir
[number
];
218 dim
[number
] = pkt
->get
<uint64_t>();
219 dir
[number
] = dim
[number
] & drir
;
220 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
222 bitvector
= ULL(1) << x
;
223 // Figure out which bits have changed
224 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
226 // The bit is now set and it wasn't before (set)
227 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
229 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
230 DPRINTF(Tsunami
, "dim write resulting in posting dir"
231 " interrupt to cpu %d\n", number
);
233 else if ((olddir
& bitvector
) &&
234 !(dir
[number
] & bitvector
))
236 // The bit was set and now its now clear and
237 // we were interrupting on that bit before
238 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
239 DPRINTF(Tsunami
, "dim write resulting in clear"
240 " dir interrupt to cpu %d\n", number
);
250 panic("TSDEV_CC_CSR write\n");
252 panic("TSDEV_CC_MTR write not implemented\n");
255 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
256 //If it is bit 12-15, this is an IPI post
259 supportedWrite
= true;
262 //If it is bit 8-11, this is an IPI clear
264 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
267 supportedWrite
= true;
270 //If it is the 4-7th bit, clear the RTC interrupt
272 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
275 supportedWrite
= true;
279 if (pkt
->get
<uint64_t>() & 0x10000000)
280 supportedWrite
= true;
283 panic("TSDEV_CC_MISC write not implemented\n");
290 panic("TSDEV_CC_AARx write not implemeted\n");
296 if(regnum
== TSDEV_CC_DIM0
)
298 else if(regnum
== TSDEV_CC_DIM1
)
300 else if(regnum
== TSDEV_CC_DIM2
)
309 olddim
= dim
[number
];
310 olddir
= dir
[number
];
311 dim
[number
] = pkt
->get
<uint64_t>();
312 dir
[number
] = dim
[number
] & drir
;
313 for(int x
= 0; x
< 64; x
++)
315 bitvector
= ULL(1) << x
;
316 // Figure out which bits have changed
317 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
319 // The bit is now set and it wasn't before (set)
320 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
322 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
323 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
325 else if ((olddir
& bitvector
) &&
326 !(dir
[number
] & bitvector
))
328 // The bit was set and now its now clear and
329 // we were interrupting on that bit before
330 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
331 DPRINTF(Tsunami
, "dim write resulting in clear"
332 " dir interrupt to cpu %d\n",
345 panic("TSDEV_CC_DIR write not implemented\n");
347 panic("TSDEV_CC_DRIR write not implemented\n");
349 panic("TSDEV_CC_PRBEN write not implemented\n");
354 panic("TSDEV_CC_IICx write not implemented\n");
359 panic("TSDEV_CC_MPRx write not implemented\n");
361 clearIPI(pkt
->get
<uint64_t>());
364 clearITI(pkt
->get
<uint64_t>());
367 reqIPI(pkt
->get
<uint64_t>());
370 panic("default in cchip read reached, accessing 0x%x\n");
372 } // not BIG_TSUNAMI write
373 pkt
->makeAtomicResponse();
378 TsunamiCChip::clearIPI(uint64_t ipintr
)
380 int numcpus
= sys
->threadContexts
.size();
381 assert(numcpus
<= Tsunami::Max_CPUs
);
384 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
385 // Check each cpu bit
386 uint64_t cpumask
= ULL(1) << cpunum
;
387 if (ipintr
& cpumask
) {
388 // Check if there is a pending ipi
389 if (ipint
& cpumask
) {
391 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
392 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
395 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
400 panic("Big IPI Clear, but not processors indicated\n");
404 TsunamiCChip::clearITI(uint64_t itintr
)
406 int numcpus
= sys
->threadContexts
.size();
407 assert(numcpus
<= Tsunami::Max_CPUs
);
410 for (int i
=0; i
< numcpus
; i
++) {
411 uint64_t cpumask
= ULL(1) << i
;
412 if (itintr
& cpumask
& itint
) {
413 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
415 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
420 panic("Big ITI Clear, but not processors indicated\n");
424 TsunamiCChip::reqIPI(uint64_t ipreq
)
426 int numcpus
= sys
->threadContexts
.size();
427 assert(numcpus
<= Tsunami::Max_CPUs
);
430 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
431 // Check each cpu bit
432 uint64_t cpumask
= ULL(1) << cpunum
;
433 if (ipreq
& cpumask
) {
434 // Check if there is already an ipi (bits 8:11)
435 if (!(ipint
& cpumask
)) {
437 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
438 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
441 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
446 panic("Big IPI Request, but not processors indicated\n");
451 TsunamiCChip::postRTC()
453 int size
= sys
->threadContexts
.size();
454 assert(size
<= Tsunami::Max_CPUs
);
456 for (int i
= 0; i
< size
; i
++) {
457 uint64_t cpumask
= ULL(1) << i
;
458 if (!(cpumask
& itint
)) {
460 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
461 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d\n", i
);
468 TsunamiCChip::postDRIR(uint32_t interrupt
)
470 uint64_t bitvector
= ULL(1) << interrupt
;
471 uint64_t size
= sys
->threadContexts
.size();
472 assert(size
<= Tsunami::Max_CPUs
);
475 for(int i
=0; i
< size
; i
++) {
476 dir
[i
] = dim
[i
] & drir
;
477 if (dim
[i
] & bitvector
) {
478 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
479 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
480 "interrupt %d\n",i
, interrupt
);
486 TsunamiCChip::clearDRIR(uint32_t interrupt
)
488 uint64_t bitvector
= ULL(1) << interrupt
;
489 uint64_t size
= sys
->threadContexts
.size();
490 assert(size
<= Tsunami::Max_CPUs
);
492 if (drir
& bitvector
)
495 for(int i
=0; i
< size
; i
++) {
496 if (dir
[i
] & bitvector
) {
497 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
498 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
499 "interrupt %d\n",i
, interrupt
);
502 dir
[i
] = dim
[i
] & drir
;
506 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
511 TsunamiCChip::serialize(std::ostream
&os
)
513 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
514 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
515 SERIALIZE_SCALAR(ipint
);
516 SERIALIZE_SCALAR(itint
);
517 SERIALIZE_SCALAR(drir
);
521 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
523 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
524 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
525 UNSERIALIZE_SCALAR(ipint
);
526 UNSERIALIZE_SCALAR(itint
);
527 UNSERIALIZE_SCALAR(drir
);
531 TsunamiCChipParams::create()
533 return new TsunamiCChip(this);