2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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33 * Emulation of the Tsunami CChip CSRs
40 #include "arch/alpha/ev5.hh"
41 #include "base/trace.hh"
42 #include "config/the_isa.hh"
43 #include "cpu/intr_control.hh"
44 #include "cpu/thread_context.hh"
45 #include "debug/IPI.hh"
46 #include "debug/Tsunami.hh"
47 #include "dev/alpha/tsunami.hh"
48 #include "dev/alpha/tsunami_cchip.hh"
49 #include "dev/alpha/tsunamireg.h"
50 #include "mem/packet.hh"
51 #include "mem/packet_access.hh"
52 #include "mem/port.hh"
53 #include "params/TsunamiCChip.hh"
54 #include "sim/system.hh"
56 //Should this be AlphaISA?
57 using namespace TheISA
;
59 TsunamiCChip::TsunamiCChip(const Params
*p
)
60 : BasicPioDevice(p
, 0x10000000), tsunami(p
->tsunami
)
66 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
72 //Put back pointer in tsunami
73 tsunami
->cchip
= this;
77 TsunamiCChip::read(PacketPtr pkt
)
79 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
81 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
83 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
84 Addr daddr
= (pkt
->getAddr() - pioAddr
);
86 switch (pkt
->getSize()) {
88 case sizeof(uint64_t):
89 pkt
->set
<uint64_t>(0);
91 if (daddr
& TSDEV_CC_BDIMS
)
93 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
97 if (daddr
& TSDEV_CC_BDIRS
)
99 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
108 panic("TSDEV_CC_MTR not implemeted\n");
111 pkt
->set(((ipint
<< 8) & 0xF) | ((itint
<< 4) & 0xF) |
112 (pkt
->req
->contextId() & 0x3));
113 // currently, FS cannot handle MT so contextId and
114 // cpuId are effectively the same, don't know if it will
115 // matter if FS becomes MT enabled. I suspect no because
116 // we are currently able to boot up to 64 procs anyway
117 // which would render the CPUID of this register useless
154 panic("TSDEV_CC_PRBEN not implemented\n");
160 panic("TSDEV_CC_IICx not implemented\n");
166 panic("TSDEV_CC_MPRx not implemented\n");
175 panic("default in cchip read reached, accessing 0x%x\n");
179 case sizeof(uint32_t):
180 case sizeof(uint16_t):
181 case sizeof(uint8_t):
183 panic("invalid access size(?) for tsunami register!\n");
185 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
186 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
188 pkt
->makeAtomicResponse();
193 TsunamiCChip::write(PacketPtr pkt
)
195 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
196 Addr daddr
= pkt
->getAddr() - pioAddr
;
197 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
200 assert(pkt
->getSize() == sizeof(uint64_t));
202 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
204 bool supportedWrite
= false;
207 if (daddr
& TSDEV_CC_BDIMS
)
209 int number
= (daddr
>> 4) & 0x3F;
215 olddim
= dim
[number
];
216 olddir
= dir
[number
];
217 dim
[number
] = pkt
->get
<uint64_t>();
218 dir
[number
] = dim
[number
] & drir
;
219 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
221 bitvector
= ULL(1) << x
;
222 // Figure out which bits have changed
223 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
225 // The bit is now set and it wasn't before (set)
226 if ((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
228 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
229 DPRINTF(Tsunami
, "dim write resulting in posting dir"
230 " interrupt to cpu %d\n", number
);
232 else if ((olddir
& bitvector
) &&
233 !(dir
[number
] & bitvector
))
235 // The bit was set and now its now clear and
236 // we were interrupting on that bit before
237 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
238 DPRINTF(Tsunami
, "dim write resulting in clear"
239 " dir interrupt to cpu %d\n", number
);
249 panic("TSDEV_CC_CSR write\n");
251 panic("TSDEV_CC_MTR write not implemented\n");
254 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
255 //If it is bit 12-15, this is an IPI post
258 supportedWrite
= true;
261 //If it is bit 8-11, this is an IPI clear
263 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
266 supportedWrite
= true;
269 //If it is the 4-7th bit, clear the RTC interrupt
271 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
274 supportedWrite
= true;
278 if (pkt
->get
<uint64_t>() & 0x10000000)
279 supportedWrite
= true;
282 panic("TSDEV_CC_MISC write not implemented\n");
289 panic("TSDEV_CC_AARx write not implemeted\n");
295 if (regnum
== TSDEV_CC_DIM0
)
297 else if (regnum
== TSDEV_CC_DIM1
)
299 else if (regnum
== TSDEV_CC_DIM2
)
308 olddim
= dim
[number
];
309 olddir
= dir
[number
];
310 dim
[number
] = pkt
->get
<uint64_t>();
311 dir
[number
] = dim
[number
] & drir
;
312 for (int x
= 0; x
< 64; x
++)
314 bitvector
= ULL(1) << x
;
315 // Figure out which bits have changed
316 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
318 // The bit is now set and it wasn't before (set)
319 if ((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
321 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
322 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
324 else if ((olddir
& bitvector
) &&
325 !(dir
[number
] & bitvector
))
327 // The bit was set and now its now clear and
328 // we were interrupting on that bit before
329 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
330 DPRINTF(Tsunami
, "dim write resulting in clear"
331 " dir interrupt to cpu %d\n",
344 panic("TSDEV_CC_DIR write not implemented\n");
346 panic("TSDEV_CC_DRIR write not implemented\n");
348 panic("TSDEV_CC_PRBEN write not implemented\n");
353 panic("TSDEV_CC_IICx write not implemented\n");
358 panic("TSDEV_CC_MPRx write not implemented\n");
360 clearIPI(pkt
->get
<uint64_t>());
363 clearITI(pkt
->get
<uint64_t>());
366 reqIPI(pkt
->get
<uint64_t>());
369 panic("default in cchip read reached, accessing 0x%x\n");
371 } // not BIG_TSUNAMI write
372 pkt
->makeAtomicResponse();
377 TsunamiCChip::clearIPI(uint64_t ipintr
)
379 int numcpus
= sys
->threadContexts
.size();
380 assert(numcpus
<= Tsunami::Max_CPUs
);
383 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
384 // Check each cpu bit
385 uint64_t cpumask
= ULL(1) << cpunum
;
386 if (ipintr
& cpumask
) {
387 // Check if there is a pending ipi
388 if (ipint
& cpumask
) {
390 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
391 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
394 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
399 panic("Big IPI Clear, but not processors indicated\n");
403 TsunamiCChip::clearITI(uint64_t itintr
)
405 int numcpus
= sys
->threadContexts
.size();
406 assert(numcpus
<= Tsunami::Max_CPUs
);
409 for (int i
=0; i
< numcpus
; i
++) {
410 uint64_t cpumask
= ULL(1) << i
;
411 if (itintr
& cpumask
& itint
) {
412 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
414 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
419 panic("Big ITI Clear, but not processors indicated\n");
423 TsunamiCChip::reqIPI(uint64_t ipreq
)
425 int numcpus
= sys
->threadContexts
.size();
426 assert(numcpus
<= Tsunami::Max_CPUs
);
429 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
430 // Check each cpu bit
431 uint64_t cpumask
= ULL(1) << cpunum
;
432 if (ipreq
& cpumask
) {
433 // Check if there is already an ipi (bits 8:11)
434 if (!(ipint
& cpumask
)) {
436 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
437 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
440 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
445 panic("Big IPI Request, but not processors indicated\n");
450 TsunamiCChip::postRTC()
452 int size
= sys
->threadContexts
.size();
453 assert(size
<= Tsunami::Max_CPUs
);
455 for (int i
= 0; i
< size
; i
++) {
456 uint64_t cpumask
= ULL(1) << i
;
457 if (!(cpumask
& itint
)) {
459 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
460 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d\n", i
);
467 TsunamiCChip::postDRIR(uint32_t interrupt
)
469 uint64_t bitvector
= ULL(1) << interrupt
;
470 uint64_t size
= sys
->threadContexts
.size();
471 assert(size
<= Tsunami::Max_CPUs
);
474 for (int i
=0; i
< size
; i
++) {
475 dir
[i
] = dim
[i
] & drir
;
476 if (dim
[i
] & bitvector
) {
477 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
478 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
479 "interrupt %d\n",i
, interrupt
);
485 TsunamiCChip::clearDRIR(uint32_t interrupt
)
487 uint64_t bitvector
= ULL(1) << interrupt
;
488 uint64_t size
= sys
->threadContexts
.size();
489 assert(size
<= Tsunami::Max_CPUs
);
491 if (drir
& bitvector
)
494 for (int i
=0; i
< size
; i
++) {
495 if (dir
[i
] & bitvector
) {
496 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
497 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
498 "interrupt %d\n",i
, interrupt
);
501 dir
[i
] = dim
[i
] & drir
;
505 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
510 TsunamiCChip::serialize(CheckpointOut
&cp
) const
512 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
513 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
514 SERIALIZE_SCALAR(ipint
);
515 SERIALIZE_SCALAR(itint
);
516 SERIALIZE_SCALAR(drir
);
520 TsunamiCChip::unserialize(CheckpointIn
&cp
)
522 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
523 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
524 UNSERIALIZE_SCALAR(ipint
);
525 UNSERIALIZE_SCALAR(itint
);
526 UNSERIALIZE_SCALAR(drir
);
530 TsunamiCChipParams::create()
532 return new TsunamiCChip(this);