2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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9 * redistributions in binary form must reproduce the above copyright
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * Emulation of the Tsunami CChip CSRs
40 #include "arch/alpha/ev5.hh"
41 #include "base/trace.hh"
42 #include "cpu/intr_control.hh"
43 #include "cpu/thread_context.hh"
44 #include "dev/alpha/tsunami.hh"
45 #include "dev/alpha/tsunami_cchip.hh"
46 #include "dev/alpha/tsunamireg.h"
47 #include "mem/packet.hh"
48 #include "mem/packet_access.hh"
49 #include "mem/port.hh"
50 #include "sim/builder.hh"
51 #include "sim/system.hh"
54 //Should this be AlphaISA?
55 using namespace TheISA
;
57 TsunamiCChip::TsunamiCChip(Params
*p
)
58 : BasicPioDevice(p
), tsunami(p
->tsunami
)
66 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
72 //Put back pointer in tsunami
73 tsunami
->cchip
= this;
77 TsunamiCChip::read(PacketPtr pkt
)
79 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
81 assert(pkt
->result
== Packet::Unknown
);
82 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
84 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
85 Addr daddr
= (pkt
->getAddr() - pioAddr
);
88 switch (pkt
->getSize()) {
90 case sizeof(uint64_t):
91 if (daddr
& TSDEV_CC_BDIMS
)
93 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
97 if (daddr
& TSDEV_CC_BDIRS
)
99 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
108 panic("TSDEV_CC_MTR not implemeted\n");
111 pkt
->set((ipint
<< 8) & 0xF | (itint
<< 4) & 0xF |
112 (pkt
->req
->getCpuNum() & 0x3));
148 panic("TSDEV_CC_PRBEN not implemented\n");
154 panic("TSDEV_CC_IICx not implemented\n");
160 panic("TSDEV_CC_MPRx not implemented\n");
169 panic("default in cchip read reached, accessing 0x%x\n");
173 case sizeof(uint32_t):
174 case sizeof(uint16_t):
175 case sizeof(uint8_t):
177 panic("invalid access size(?) for tsunami register!\n");
179 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
180 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
182 pkt
->result
= Packet::Success
;
187 TsunamiCChip::write(PacketPtr pkt
)
189 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
190 Addr daddr
= pkt
->getAddr() - pioAddr
;
191 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
194 assert(pkt
->getSize() == sizeof(uint64_t));
196 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
198 bool supportedWrite
= false;
201 if (daddr
& TSDEV_CC_BDIMS
)
203 int number
= (daddr
>> 4) & 0x3F;
209 olddim
= dim
[number
];
210 olddir
= dir
[number
];
211 dim
[number
] = pkt
->get
<uint64_t>();
212 dir
[number
] = dim
[number
] & drir
;
213 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
215 bitvector
= ULL(1) << x
;
216 // Figure out which bits have changed
217 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
219 // The bit is now set and it wasn't before (set)
220 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
222 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
223 DPRINTF(Tsunami
, "dim write resulting in posting dir"
224 " interrupt to cpu %d\n", number
);
226 else if ((olddir
& bitvector
) &&
227 !(dir
[number
] & bitvector
))
229 // The bit was set and now its now clear and
230 // we were interrupting on that bit before
231 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
232 DPRINTF(Tsunami
, "dim write resulting in clear"
233 " dir interrupt to cpu %d\n", number
);
243 panic("TSDEV_CC_CSR write\n");
245 panic("TSDEV_CC_MTR write not implemented\n");
248 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
249 //If it is bit 12-15, this is an IPI post
252 supportedWrite
= true;
255 //If it is bit 8-11, this is an IPI clear
257 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
260 supportedWrite
= true;
263 //If it is the 4-7th bit, clear the RTC interrupt
265 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
268 supportedWrite
= true;
272 if (pkt
->get
<uint64_t>() & 0x10000000)
273 supportedWrite
= true;
276 panic("TSDEV_CC_MISC write not implemented\n");
283 panic("TSDEV_CC_AARx write not implemeted\n");
289 if(regnum
== TSDEV_CC_DIM0
)
291 else if(regnum
== TSDEV_CC_DIM1
)
293 else if(regnum
== TSDEV_CC_DIM2
)
302 olddim
= dim
[number
];
303 olddir
= dir
[number
];
304 dim
[number
] = pkt
->get
<uint64_t>();
305 dir
[number
] = dim
[number
] & drir
;
306 for(int x
= 0; x
< 64; x
++)
308 bitvector
= ULL(1) << x
;
309 // Figure out which bits have changed
310 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
312 // The bit is now set and it wasn't before (set)
313 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
315 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
316 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
318 else if ((olddir
& bitvector
) &&
319 !(dir
[number
] & bitvector
))
321 // The bit was set and now its now clear and
322 // we were interrupting on that bit before
323 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
324 DPRINTF(Tsunami
, "dim write resulting in clear"
325 " dir interrupt to cpu %d\n",
338 panic("TSDEV_CC_DIR write not implemented\n");
340 panic("TSDEV_CC_DRIR write not implemented\n");
342 panic("TSDEV_CC_PRBEN write not implemented\n");
347 panic("TSDEV_CC_IICx write not implemented\n");
352 panic("TSDEV_CC_MPRx write not implemented\n");
354 clearIPI(pkt
->get
<uint64_t>());
357 clearITI(pkt
->get
<uint64_t>());
360 reqIPI(pkt
->get
<uint64_t>());
363 panic("default in cchip read reached, accessing 0x%x\n");
365 } // not BIG_TSUNAMI write
366 pkt
->result
= Packet::Success
;
371 TsunamiCChip::clearIPI(uint64_t ipintr
)
373 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
374 assert(numcpus
<= Tsunami::Max_CPUs
);
377 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
378 // Check each cpu bit
379 uint64_t cpumask
= ULL(1) << cpunum
;
380 if (ipintr
& cpumask
) {
381 // Check if there is a pending ipi
382 if (ipint
& cpumask
) {
384 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
385 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
388 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
393 panic("Big IPI Clear, but not processors indicated\n");
397 TsunamiCChip::clearITI(uint64_t itintr
)
399 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
400 assert(numcpus
<= Tsunami::Max_CPUs
);
403 for (int i
=0; i
< numcpus
; i
++) {
404 uint64_t cpumask
= ULL(1) << i
;
405 if (itintr
& cpumask
& itint
) {
406 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
408 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
413 panic("Big ITI Clear, but not processors indicated\n");
417 TsunamiCChip::reqIPI(uint64_t ipreq
)
419 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
420 assert(numcpus
<= Tsunami::Max_CPUs
);
423 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
424 // Check each cpu bit
425 uint64_t cpumask
= ULL(1) << cpunum
;
426 if (ipreq
& cpumask
) {
427 // Check if there is already an ipi (bits 8:11)
428 if (!(ipint
& cpumask
)) {
430 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
431 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
434 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
439 panic("Big IPI Request, but not processors indicated\n");
444 TsunamiCChip::postRTC()
446 int size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
447 assert(size
<= Tsunami::Max_CPUs
);
449 for (int i
= 0; i
< size
; i
++) {
450 uint64_t cpumask
= ULL(1) << i
;
451 if (!(cpumask
& itint
)) {
453 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
454 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d", i
);
461 TsunamiCChip::postDRIR(uint32_t interrupt
)
463 uint64_t bitvector
= ULL(1) << interrupt
;
464 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
465 assert(size
<= Tsunami::Max_CPUs
);
468 for(int i
=0; i
< size
; i
++) {
469 dir
[i
] = dim
[i
] & drir
;
470 if (dim
[i
] & bitvector
) {
471 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
472 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
473 "interrupt %d\n",i
, interrupt
);
479 TsunamiCChip::clearDRIR(uint32_t interrupt
)
481 uint64_t bitvector
= ULL(1) << interrupt
;
482 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
483 assert(size
<= Tsunami::Max_CPUs
);
485 if (drir
& bitvector
)
488 for(int i
=0; i
< size
; i
++) {
489 if (dir
[i
] & bitvector
) {
490 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
491 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
492 "interrupt %d\n",i
, interrupt
);
495 dir
[i
] = dim
[i
] & drir
;
499 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
504 TsunamiCChip::serialize(std::ostream
&os
)
506 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
507 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
508 SERIALIZE_SCALAR(ipint
);
509 SERIALIZE_SCALAR(itint
);
510 SERIALIZE_SCALAR(drir
);
514 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
516 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
517 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
518 UNSERIALIZE_SCALAR(ipint
);
519 UNSERIALIZE_SCALAR(itint
);
520 UNSERIALIZE_SCALAR(drir
);
523 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
525 Param
<Addr
> pio_addr
;
526 Param
<Tick
> pio_latency
;
527 SimObjectParam
<Platform
*> platform
;
528 SimObjectParam
<System
*> system
;
529 SimObjectParam
<Tsunami
*> tsunami
;
531 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
533 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
535 INIT_PARAM(pio_addr
, "Device Address"),
536 INIT_PARAM(pio_latency
, "Programmed IO latency"),
537 INIT_PARAM(platform
, "platform"),
538 INIT_PARAM(system
, "system object"),
539 INIT_PARAM(tsunami
, "Tsunami")
541 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
543 CREATE_SIM_OBJECT(TsunamiCChip
)
545 TsunamiCChip::Params
*p
= new TsunamiCChip::Params
;
546 p
->name
= getInstanceName();
547 p
->pio_addr
= pio_addr
;
548 p
->pio_delay
= pio_latency
;
549 p
->platform
= platform
;
551 p
->tsunami
= tsunami
;
552 return new TsunamiCChip(p
);
555 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip
)