src/dev/alpha/tsunami_cchip.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  *          Ron Dreslinski
  30  */
  31
  32 /** @file
  33  * Emulation of the Tsunami CChip CSRs
  34  */
  35
  36 #include <deque>
  37 #include <string>
  38 #include <vector>
  39
  40 #include "arch/alpha/ev5.hh"
  41 #include "base/trace.hh"
  42 #include "cpu/intr_control.hh"
  43 #include "cpu/thread_context.hh"
  44 #include "dev/alpha/tsunami.hh"
  45 #include "dev/alpha/tsunami_cchip.hh"
  46 #include "dev/alpha/tsunamireg.h"
  47 #include "mem/packet.hh"
  48 #include "mem/packet_access.hh"
  49 #include "mem/port.hh"
  50 #include "sim/builder.hh"
  51 #include "sim/system.hh"
  52
  53 using namespace std;
  54 //Should this be AlphaISA?
  55 using namespace TheISA;
  56
  57 TsunamiCChip::TsunamiCChip(Params *p)
  58     : BasicPioDevice(p), tsunami(p->tsunami)
  59 {
  60     pioSize = 0x10000000;
  61
  62     drir = 0;
  63     ipint = 0;
  64     itint = 0;
  65
  66     for (int x = 0; x < Tsunami::Max_CPUs; x++)
  67     {
  68         dim[x] = 0;
  69         dir[x] = 0;
  70     }
  71
  72     //Put back pointer in tsunami
  73     tsunami->cchip = this;
  74 }
  75
  76 Tick
  77 TsunamiCChip::read(PacketPtr pkt)
  78 {
  79     DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
  80
  81     assert(pkt->result == Packet::Unknown);
  82     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  83
  84     Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
  85     Addr daddr = (pkt->getAddr() - pioAddr);
  86
  87     pkt->allocate();
  88     switch (pkt->getSize()) {
  89
  90       case sizeof(uint64_t):
  91           if (daddr & TSDEV_CC_BDIMS)
  92           {
  93               pkt->set(dim[(daddr >> 4) & 0x3F]);
  94               break;
  95           }
  96
  97           if (daddr & TSDEV_CC_BDIRS)
  98           {
  99               pkt->set(dir[(daddr >> 4) & 0x3F]);
 100               break;
 101           }
 102
 103           switch(regnum) {
 104               case TSDEV_CC_CSR:
 105                   pkt->set(0x0);
 106                   break;
 107               case TSDEV_CC_MTR:
 108                   panic("TSDEV_CC_MTR not implemeted\n");
 109                    break;
 110               case TSDEV_CC_MISC:
 111                   pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
 112                                      (pkt->req->getCpuNum() & 0x3));
 113                   break;
 114               case TSDEV_CC_AAR0:
 115               case TSDEV_CC_AAR1:
 116               case TSDEV_CC_AAR2:
 117               case TSDEV_CC_AAR3:
 118                   pkt->set(0);
 119                   break;
 120               case TSDEV_CC_DIM0:
 121                   pkt->set(dim[0]);
 122                   break;
 123               case TSDEV_CC_DIM1:
 124                   pkt->set(dim[1]);
 125                   break;
 126               case TSDEV_CC_DIM2:
 127                   pkt->set(dim[2]);
 128                   break;
 129               case TSDEV_CC_DIM3:
 130                   pkt->set(dim[3]);
 131                   break;
 132               case TSDEV_CC_DIR0:
 133                   pkt->set(dir[0]);
 134                   break;
 135               case TSDEV_CC_DIR1:
 136                   pkt->set(dir[1]);
 137                   break;
 138               case TSDEV_CC_DIR2:
 139                   pkt->set(dir[2]);
 140                   break;
 141               case TSDEV_CC_DIR3:
 142                   pkt->set(dir[3]);
 143                   break;
 144               case TSDEV_CC_DRIR:
 145                   pkt->set(drir);
 146                   break;
 147               case TSDEV_CC_PRBEN:
 148                   panic("TSDEV_CC_PRBEN not implemented\n");
 149                   break;
 150               case TSDEV_CC_IIC0:
 151               case TSDEV_CC_IIC1:
 152               case TSDEV_CC_IIC2:
 153               case TSDEV_CC_IIC3:
 154                   panic("TSDEV_CC_IICx not implemented\n");
 155                   break;
 156               case TSDEV_CC_MPR0:
 157               case TSDEV_CC_MPR1:
 158               case TSDEV_CC_MPR2:
 159               case TSDEV_CC_MPR3:
 160                   panic("TSDEV_CC_MPRx not implemented\n");
 161                   break;
 162               case TSDEV_CC_IPIR:
 163                   pkt->set(ipint);
 164                   break;
 165               case TSDEV_CC_ITIR:
 166                   pkt->set(itint);
 167                   break;
 168               default:
 169                   panic("default in cchip read reached, accessing 0x%x\n");
 170            } // uint64_t
 171
 172       break;
 173       case sizeof(uint32_t):
 174       case sizeof(uint16_t):
 175       case sizeof(uint8_t):
 176       default:
 177         panic("invalid access size(?) for tsunami register!\n");
 178     }
 179     DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
 180             regnum, pkt->getSize(), pkt->get<uint64_t>());
 181
 182     pkt->result = Packet::Success;
 183     return pioDelay;
 184 }
 185
 186 Tick
 187 TsunamiCChip::write(PacketPtr pkt)
 188 {
 189     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 190     Addr daddr = pkt->getAddr() - pioAddr;
 191     Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
 192
 193
 194     assert(pkt->getSize() == sizeof(uint64_t));
 195
 196     DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
 197
 198     bool supportedWrite = false;
 199
 200
 201     if (daddr & TSDEV_CC_BDIMS)
 202     {
 203         int number = (daddr >> 4) & 0x3F;
 204
 205         uint64_t bitvector;
 206         uint64_t olddim;
 207         uint64_t olddir;
 208
 209         olddim = dim[number];
 210         olddir = dir[number];
 211         dim[number] = pkt->get<uint64_t>();
 212         dir[number] = dim[number] & drir;
 213         for(int x = 0; x < Tsunami::Max_CPUs; x++)
 214         {
 215             bitvector = ULL(1) << x;
 216             // Figure out which bits have changed
 217             if ((dim[number] & bitvector) != (olddim & bitvector))
 218             {
 219                 // The bit is now set and it wasn't before (set)
 220                 if((dim[number] & bitvector) && (dir[number] & bitvector))
 221                 {
 222                     tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 223                     DPRINTF(Tsunami, "dim write resulting in posting dir"
 224                             " interrupt to cpu %d\n", number);
 225                 }
 226                 else if ((olddir & bitvector) &&
 227                         !(dir[number] & bitvector))
 228                 {
 229                     // The bit was set and now its now clear and
 230                     // we were interrupting on that bit before
 231                     tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 232                     DPRINTF(Tsunami, "dim write resulting in clear"
 233                             " dir interrupt to cpu %d\n", number);
 234
 235                 }
 236
 237
 238             }
 239         }
 240     } else {
 241         switch(regnum) {
 242           case TSDEV_CC_CSR:
 243               panic("TSDEV_CC_CSR write\n");
 244           case TSDEV_CC_MTR:
 245               panic("TSDEV_CC_MTR write not implemented\n");
 246           case TSDEV_CC_MISC:
 247             uint64_t ipreq;
 248             ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
 249             //If it is bit 12-15, this is an IPI post
 250             if (ipreq) {
 251                 reqIPI(ipreq);
 252                 supportedWrite = true;
 253             }
 254
 255             //If it is bit 8-11, this is an IPI clear
 256             uint64_t ipintr;
 257             ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
 258             if (ipintr) {
 259                 clearIPI(ipintr);
 260                 supportedWrite = true;
 261             }
 262
 263             //If it is the 4-7th bit, clear the RTC interrupt
 264             uint64_t itintr;
 265               itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
 266             if (itintr) {
 267                   clearITI(itintr);
 268                 supportedWrite = true;
 269             }
 270
 271               // ignore NXMs
 272               if (pkt->get<uint64_t>() & 0x10000000)
 273                   supportedWrite = true;
 274
 275             if(!supportedWrite)
 276                   panic("TSDEV_CC_MISC write not implemented\n");
 277
 278             break;
 279             case TSDEV_CC_AAR0:
 280             case TSDEV_CC_AAR1:
 281             case TSDEV_CC_AAR2:
 282             case TSDEV_CC_AAR3:
 283                 panic("TSDEV_CC_AARx write not implemeted\n");
 284             case TSDEV_CC_DIM0:
 285             case TSDEV_CC_DIM1:
 286             case TSDEV_CC_DIM2:
 287             case TSDEV_CC_DIM3:
 288                 int number;
 289                 if(regnum == TSDEV_CC_DIM0)
 290                     number = 0;
 291                 else if(regnum == TSDEV_CC_DIM1)
 292                     number = 1;
 293                 else if(regnum == TSDEV_CC_DIM2)
 294                     number = 2;
 295                 else
 296                     number = 3;
 297
 298                 uint64_t bitvector;
 299                 uint64_t olddim;
 300                 uint64_t olddir;
 301
 302                 olddim = dim[number];
 303                 olddir = dir[number];
 304                 dim[number] = pkt->get<uint64_t>();
 305                 dir[number] = dim[number] & drir;
 306                 for(int x = 0; x < 64; x++)
 307                 {
 308                     bitvector = ULL(1) << x;
 309                     // Figure out which bits have changed
 310                     if ((dim[number] & bitvector) != (olddim & bitvector))
 311                     {
 312                         // The bit is now set and it wasn't before (set)
 313                         if((dim[number] & bitvector) && (dir[number] & bitvector))
 314                         {
 315                           tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 316                           DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
 317                         }
 318                         else if ((olddir & bitvector) &&
 319                                 !(dir[number] & bitvector))
 320                         {
 321                             // The bit was set and now its now clear and
 322                             // we were interrupting on that bit before
 323                             tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 324                           DPRINTF(Tsunami, "dim write resulting in clear"
 325                                     " dir interrupt to cpu %d\n",
 326                                     x);
 327
 328                         }
 329
 330
 331                     }
 332                 }
 333                 break;
 334             case TSDEV_CC_DIR0:
 335             case TSDEV_CC_DIR1:
 336             case TSDEV_CC_DIR2:
 337             case TSDEV_CC_DIR3:
 338                 panic("TSDEV_CC_DIR write not implemented\n");
 339             case TSDEV_CC_DRIR:
 340                 panic("TSDEV_CC_DRIR write not implemented\n");
 341             case TSDEV_CC_PRBEN:
 342                 panic("TSDEV_CC_PRBEN write not implemented\n");
 343             case TSDEV_CC_IIC0:
 344             case TSDEV_CC_IIC1:
 345             case TSDEV_CC_IIC2:
 346             case TSDEV_CC_IIC3:
 347                 panic("TSDEV_CC_IICx write not implemented\n");
 348             case TSDEV_CC_MPR0:
 349             case TSDEV_CC_MPR1:
 350             case TSDEV_CC_MPR2:
 351             case TSDEV_CC_MPR3:
 352                 panic("TSDEV_CC_MPRx write not implemented\n");
 353             case TSDEV_CC_IPIR:
 354                 clearIPI(pkt->get<uint64_t>());
 355                 break;
 356             case TSDEV_CC_ITIR:
 357                 clearITI(pkt->get<uint64_t>());
 358                 break;
 359             case TSDEV_CC_IPIQ:
 360                 reqIPI(pkt->get<uint64_t>());
 361                 break;
 362             default:
 363               panic("default in cchip read reached, accessing 0x%x\n");
 364         }  // swtich(regnum)
 365     } // not BIG_TSUNAMI write
 366     pkt->result = Packet::Success;
 367     return pioDelay;
 368 }
 369
 370 void
 371 TsunamiCChip::clearIPI(uint64_t ipintr)
 372 {
 373     int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
 374     assert(numcpus <= Tsunami::Max_CPUs);
 375
 376     if (ipintr) {
 377         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 378             // Check each cpu bit
 379             uint64_t cpumask = ULL(1) << cpunum;
 380             if (ipintr & cpumask) {
 381                 // Check if there is a pending ipi
 382                 if (ipint & cpumask) {
 383                     ipint &= ~cpumask;
 384                     tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 385                     DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
 386                 }
 387                 else
 388                     warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
 389             }
 390         }
 391     }
 392     else
 393         panic("Big IPI Clear, but not processors indicated\n");
 394 }
 395
 396 void
 397 TsunamiCChip::clearITI(uint64_t itintr)
 398 {
 399     int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
 400     assert(numcpus <= Tsunami::Max_CPUs);
 401
 402     if (itintr) {
 403         for (int i=0; i < numcpus; i++) {
 404             uint64_t cpumask = ULL(1) << i;
 405             if (itintr & cpumask & itint) {
 406                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
 407                 itint &= ~cpumask;
 408                 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
 409             }
 410         }
 411     }
 412     else
 413         panic("Big ITI Clear, but not processors indicated\n");
 414 }
 415
 416 void
 417 TsunamiCChip::reqIPI(uint64_t ipreq)
 418 {
 419     int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
 420     assert(numcpus <= Tsunami::Max_CPUs);
 421
 422     if (ipreq) {
 423         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 424             // Check each cpu bit
 425             uint64_t cpumask = ULL(1) << cpunum;
 426             if (ipreq & cpumask) {
 427                 // Check if there is already an ipi (bits 8:11)
 428                 if (!(ipint & cpumask)) {
 429                     ipint  |= cpumask;
 430                     tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 431                     DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
 432                 }
 433                 else
 434                     warn("post IPI for CPU=%d, but IPI already\n", cpunum);
 435             }
 436         }
 437     }
 438     else
 439         panic("Big IPI Request, but not processors indicated\n");
 440 }
 441
 442
 443 void
 444 TsunamiCChip::postRTC()
 445 {
 446     int size = tsunami->intrctrl->cpu->system->threadContexts.size();
 447     assert(size <= Tsunami::Max_CPUs);
 448
 449     for (int i = 0; i < size; i++) {
 450         uint64_t cpumask = ULL(1) << i;
 451        if (!(cpumask & itint)) {
 452            itint |= cpumask;
 453            tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
 454            DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
 455        }
 456     }
 457
 458 }
 459
 460 void
 461 TsunamiCChip::postDRIR(uint32_t interrupt)
 462 {
 463     uint64_t bitvector = ULL(1) << interrupt;
 464     uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
 465     assert(size <= Tsunami::Max_CPUs);
 466     drir |= bitvector;
 467
 468     for(int i=0; i < size; i++) {
 469         dir[i] = dim[i] & drir;
 470        if (dim[i] & bitvector) {
 471               tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
 472               DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
 473                         "interrupt %d\n",i, interrupt);
 474        }
 475     }
 476 }
 477
 478 void
 479 TsunamiCChip::clearDRIR(uint32_t interrupt)
 480 {
 481     uint64_t bitvector = ULL(1) << interrupt;
 482     uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
 483     assert(size <= Tsunami::Max_CPUs);
 484
 485     if (drir & bitvector)
 486     {
 487         drir &= ~bitvector;
 488         for(int i=0; i < size; i++) {
 489            if (dir[i] & bitvector) {
 490                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
 491                DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
 492                     "interrupt %d\n",i, interrupt);
 493
 494            }
 495            dir[i] = dim[i] & drir;
 496         }
 497     }
 498     else
 499         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 500 }
 501
 502
 503 void
 504 TsunamiCChip::serialize(std::ostream &os)
 505 {
 506     SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 507     SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 508     SERIALIZE_SCALAR(ipint);
 509     SERIALIZE_SCALAR(itint);
 510     SERIALIZE_SCALAR(drir);
 511 }
 512
 513 void
 514 TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
 515 {
 516     UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 517     UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 518     UNSERIALIZE_SCALAR(ipint);
 519     UNSERIALIZE_SCALAR(itint);
 520     UNSERIALIZE_SCALAR(drir);
 521 }
 522
 523 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 524
 525     Param<Addr> pio_addr;
 526     Param<Tick> pio_latency;
 527     SimObjectParam<Platform *> platform;
 528     SimObjectParam<System *> system;
 529     SimObjectParam<Tsunami *> tsunami;
 530
 531 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 532
 533 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 534
 535     INIT_PARAM(pio_addr, "Device Address"),
 536     INIT_PARAM(pio_latency, "Programmed IO latency"),
 537     INIT_PARAM(platform, "platform"),
 538     INIT_PARAM(system, "system object"),
 539     INIT_PARAM(tsunami, "Tsunami")
 540
 541 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 542
 543 CREATE_SIM_OBJECT(TsunamiCChip)
 544 {
 545     TsunamiCChip::Params *p = new TsunamiCChip::Params;
 546     p->name = getInstanceName();
 547     p->pio_addr = pio_addr;
 548     p->pio_delay = pio_latency;
 549     p->platform = platform;
 550     p->system = system;
 551     p->tsunami = tsunami;
 552     return new TsunamiCChip(p);
 553 }
 554
 555 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)