2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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12 * neither the name of the copyright holders nor the names of its
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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33 * Emulation of the Tsunami CChip CSRs
40 #include "arch/alpha/ev5.hh"
41 #include "base/trace.hh"
42 #include "cpu/intr_control.hh"
43 #include "cpu/thread_context.hh"
44 #include "dev/alpha/tsunami.hh"
45 #include "dev/alpha/tsunami_cchip.hh"
46 #include "dev/alpha/tsunamireg.h"
47 #include "mem/packet.hh"
48 #include "mem/packet_access.hh"
49 #include "mem/port.hh"
50 #include "params/TsunamiCChip.hh"
51 #include "sim/system.hh"
54 //Should this be AlphaISA?
55 using namespace TheISA
;
57 TsunamiCChip::TsunamiCChip(const Params
*p
)
58 : BasicPioDevice(p
), tsunami(p
->tsunami
)
66 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
72 //Put back pointer in tsunami
73 tsunami
->cchip
= this;
77 TsunamiCChip::read(PacketPtr pkt
)
79 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
81 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
83 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
84 Addr daddr
= (pkt
->getAddr() - pioAddr
);
87 switch (pkt
->getSize()) {
89 case sizeof(uint64_t):
90 pkt
->set
<uint64_t>(0);
92 if (daddr
& TSDEV_CC_BDIMS
)
94 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
98 if (daddr
& TSDEV_CC_BDIRS
)
100 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
109 panic("TSDEV_CC_MTR not implemeted\n");
112 pkt
->set(((ipint
<< 8) & 0xF) | ((itint
<< 4) & 0xF) |
113 (pkt
->req
->getCpuNum() & 0x3));
149 panic("TSDEV_CC_PRBEN not implemented\n");
155 panic("TSDEV_CC_IICx not implemented\n");
161 panic("TSDEV_CC_MPRx not implemented\n");
170 panic("default in cchip read reached, accessing 0x%x\n");
174 case sizeof(uint32_t):
175 case sizeof(uint16_t):
176 case sizeof(uint8_t):
178 panic("invalid access size(?) for tsunami register!\n");
180 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
181 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
183 pkt
->makeAtomicResponse();
188 TsunamiCChip::write(PacketPtr pkt
)
190 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
191 Addr daddr
= pkt
->getAddr() - pioAddr
;
192 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
195 assert(pkt
->getSize() == sizeof(uint64_t));
197 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
199 bool supportedWrite
= false;
202 if (daddr
& TSDEV_CC_BDIMS
)
204 int number
= (daddr
>> 4) & 0x3F;
210 olddim
= dim
[number
];
211 olddir
= dir
[number
];
212 dim
[number
] = pkt
->get
<uint64_t>();
213 dir
[number
] = dim
[number
] & drir
;
214 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
216 bitvector
= ULL(1) << x
;
217 // Figure out which bits have changed
218 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
220 // The bit is now set and it wasn't before (set)
221 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
223 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
224 DPRINTF(Tsunami
, "dim write resulting in posting dir"
225 " interrupt to cpu %d\n", number
);
227 else if ((olddir
& bitvector
) &&
228 !(dir
[number
] & bitvector
))
230 // The bit was set and now its now clear and
231 // we were interrupting on that bit before
232 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
233 DPRINTF(Tsunami
, "dim write resulting in clear"
234 " dir interrupt to cpu %d\n", number
);
244 panic("TSDEV_CC_CSR write\n");
246 panic("TSDEV_CC_MTR write not implemented\n");
249 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
250 //If it is bit 12-15, this is an IPI post
253 supportedWrite
= true;
256 //If it is bit 8-11, this is an IPI clear
258 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
261 supportedWrite
= true;
264 //If it is the 4-7th bit, clear the RTC interrupt
266 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
269 supportedWrite
= true;
273 if (pkt
->get
<uint64_t>() & 0x10000000)
274 supportedWrite
= true;
277 panic("TSDEV_CC_MISC write not implemented\n");
284 panic("TSDEV_CC_AARx write not implemeted\n");
290 if(regnum
== TSDEV_CC_DIM0
)
292 else if(regnum
== TSDEV_CC_DIM1
)
294 else if(regnum
== TSDEV_CC_DIM2
)
303 olddim
= dim
[number
];
304 olddir
= dir
[number
];
305 dim
[number
] = pkt
->get
<uint64_t>();
306 dir
[number
] = dim
[number
] & drir
;
307 for(int x
= 0; x
< 64; x
++)
309 bitvector
= ULL(1) << x
;
310 // Figure out which bits have changed
311 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
313 // The bit is now set and it wasn't before (set)
314 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
316 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
317 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
319 else if ((olddir
& bitvector
) &&
320 !(dir
[number
] & bitvector
))
322 // The bit was set and now its now clear and
323 // we were interrupting on that bit before
324 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
325 DPRINTF(Tsunami
, "dim write resulting in clear"
326 " dir interrupt to cpu %d\n",
339 panic("TSDEV_CC_DIR write not implemented\n");
341 panic("TSDEV_CC_DRIR write not implemented\n");
343 panic("TSDEV_CC_PRBEN write not implemented\n");
348 panic("TSDEV_CC_IICx write not implemented\n");
353 panic("TSDEV_CC_MPRx write not implemented\n");
355 clearIPI(pkt
->get
<uint64_t>());
358 clearITI(pkt
->get
<uint64_t>());
361 reqIPI(pkt
->get
<uint64_t>());
364 panic("default in cchip read reached, accessing 0x%x\n");
366 } // not BIG_TSUNAMI write
367 pkt
->makeAtomicResponse();
372 TsunamiCChip::clearIPI(uint64_t ipintr
)
374 int numcpus
= sys
->threadContexts
.size();
375 assert(numcpus
<= Tsunami::Max_CPUs
);
378 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
379 // Check each cpu bit
380 uint64_t cpumask
= ULL(1) << cpunum
;
381 if (ipintr
& cpumask
) {
382 // Check if there is a pending ipi
383 if (ipint
& cpumask
) {
385 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
386 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
389 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
394 panic("Big IPI Clear, but not processors indicated\n");
398 TsunamiCChip::clearITI(uint64_t itintr
)
400 int numcpus
= sys
->threadContexts
.size();
401 assert(numcpus
<= Tsunami::Max_CPUs
);
404 for (int i
=0; i
< numcpus
; i
++) {
405 uint64_t cpumask
= ULL(1) << i
;
406 if (itintr
& cpumask
& itint
) {
407 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
409 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
414 panic("Big ITI Clear, but not processors indicated\n");
418 TsunamiCChip::reqIPI(uint64_t ipreq
)
420 int numcpus
= sys
->threadContexts
.size();
421 assert(numcpus
<= Tsunami::Max_CPUs
);
424 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
425 // Check each cpu bit
426 uint64_t cpumask
= ULL(1) << cpunum
;
427 if (ipreq
& cpumask
) {
428 // Check if there is already an ipi (bits 8:11)
429 if (!(ipint
& cpumask
)) {
431 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
432 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
435 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
440 panic("Big IPI Request, but not processors indicated\n");
445 TsunamiCChip::postRTC()
447 int size
= sys
->threadContexts
.size();
448 assert(size
<= Tsunami::Max_CPUs
);
450 for (int i
= 0; i
< size
; i
++) {
451 uint64_t cpumask
= ULL(1) << i
;
452 if (!(cpumask
& itint
)) {
454 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
455 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d\n", i
);
462 TsunamiCChip::postDRIR(uint32_t interrupt
)
464 uint64_t bitvector
= ULL(1) << interrupt
;
465 uint64_t size
= sys
->threadContexts
.size();
466 assert(size
<= Tsunami::Max_CPUs
);
469 for(int i
=0; i
< size
; i
++) {
470 dir
[i
] = dim
[i
] & drir
;
471 if (dim
[i
] & bitvector
) {
472 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
473 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
474 "interrupt %d\n",i
, interrupt
);
480 TsunamiCChip::clearDRIR(uint32_t interrupt
)
482 uint64_t bitvector
= ULL(1) << interrupt
;
483 uint64_t size
= sys
->threadContexts
.size();
484 assert(size
<= Tsunami::Max_CPUs
);
486 if (drir
& bitvector
)
489 for(int i
=0; i
< size
; i
++) {
490 if (dir
[i
] & bitvector
) {
491 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
492 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
493 "interrupt %d\n",i
, interrupt
);
496 dir
[i
] = dim
[i
] & drir
;
500 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
505 TsunamiCChip::serialize(std::ostream
&os
)
507 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
508 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
509 SERIALIZE_SCALAR(ipint
);
510 SERIALIZE_SCALAR(itint
);
511 SERIALIZE_SCALAR(drir
);
515 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
517 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
518 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
519 UNSERIALIZE_SCALAR(ipint
);
520 UNSERIALIZE_SCALAR(itint
);
521 UNSERIALIZE_SCALAR(drir
);
525 TsunamiCChipParams::create()
527 return new TsunamiCChip(this);