2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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33 * Emulation of the Tsunami CChip CSRs
40 #include "arch/alpha/ev5.hh"
41 #include "base/trace.hh"
42 #include "cpu/intr_control.hh"
43 #include "cpu/thread_context.hh"
44 #include "dev/alpha/tsunami.hh"
45 #include "dev/alpha/tsunami_cchip.hh"
46 #include "dev/alpha/tsunamireg.h"
47 #include "mem/packet.hh"
48 #include "mem/packet_access.hh"
49 #include "mem/port.hh"
50 #include "sim/builder.hh"
51 #include "sim/system.hh"
54 //Should this be AlphaISA?
55 using namespace TheISA
;
57 TsunamiCChip::TsunamiCChip(Params
*p
)
58 : BasicPioDevice(p
), tsunami(p
->tsunami
)
66 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
72 //Put back pointer in tsunami
73 tsunami
->cchip
= this;
77 TsunamiCChip::read(PacketPtr pkt
)
79 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
81 assert(pkt
->result
== Packet::Unknown
);
82 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
84 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
85 Addr daddr
= (pkt
->getAddr() - pioAddr
);
88 switch (pkt
->getSize()) {
90 case sizeof(uint64_t):
91 pkt
->set
<uint64_t>(0);
93 if (daddr
& TSDEV_CC_BDIMS
)
95 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
99 if (daddr
& TSDEV_CC_BDIRS
)
101 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
110 panic("TSDEV_CC_MTR not implemeted\n");
113 pkt
->set((ipint
<< 8) & 0xF | (itint
<< 4) & 0xF |
114 (pkt
->req
->getCpuNum() & 0x3));
150 panic("TSDEV_CC_PRBEN not implemented\n");
156 panic("TSDEV_CC_IICx not implemented\n");
162 panic("TSDEV_CC_MPRx not implemented\n");
171 panic("default in cchip read reached, accessing 0x%x\n");
175 case sizeof(uint32_t):
176 case sizeof(uint16_t):
177 case sizeof(uint8_t):
179 panic("invalid access size(?) for tsunami register!\n");
181 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
182 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
184 pkt
->result
= Packet::Success
;
189 TsunamiCChip::write(PacketPtr pkt
)
191 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
192 Addr daddr
= pkt
->getAddr() - pioAddr
;
193 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
196 assert(pkt
->getSize() == sizeof(uint64_t));
198 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
200 bool supportedWrite
= false;
203 if (daddr
& TSDEV_CC_BDIMS
)
205 int number
= (daddr
>> 4) & 0x3F;
211 olddim
= dim
[number
];
212 olddir
= dir
[number
];
213 dim
[number
] = pkt
->get
<uint64_t>();
214 dir
[number
] = dim
[number
] & drir
;
215 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
217 bitvector
= ULL(1) << x
;
218 // Figure out which bits have changed
219 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
221 // The bit is now set and it wasn't before (set)
222 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
224 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
225 DPRINTF(Tsunami
, "dim write resulting in posting dir"
226 " interrupt to cpu %d\n", number
);
228 else if ((olddir
& bitvector
) &&
229 !(dir
[number
] & bitvector
))
231 // The bit was set and now its now clear and
232 // we were interrupting on that bit before
233 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
234 DPRINTF(Tsunami
, "dim write resulting in clear"
235 " dir interrupt to cpu %d\n", number
);
245 panic("TSDEV_CC_CSR write\n");
247 panic("TSDEV_CC_MTR write not implemented\n");
250 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
251 //If it is bit 12-15, this is an IPI post
254 supportedWrite
= true;
257 //If it is bit 8-11, this is an IPI clear
259 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
262 supportedWrite
= true;
265 //If it is the 4-7th bit, clear the RTC interrupt
267 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
270 supportedWrite
= true;
274 if (pkt
->get
<uint64_t>() & 0x10000000)
275 supportedWrite
= true;
278 panic("TSDEV_CC_MISC write not implemented\n");
285 panic("TSDEV_CC_AARx write not implemeted\n");
291 if(regnum
== TSDEV_CC_DIM0
)
293 else if(regnum
== TSDEV_CC_DIM1
)
295 else if(regnum
== TSDEV_CC_DIM2
)
304 olddim
= dim
[number
];
305 olddir
= dir
[number
];
306 dim
[number
] = pkt
->get
<uint64_t>();
307 dir
[number
] = dim
[number
] & drir
;
308 for(int x
= 0; x
< 64; x
++)
310 bitvector
= ULL(1) << x
;
311 // Figure out which bits have changed
312 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
314 // The bit is now set and it wasn't before (set)
315 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
317 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
318 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
320 else if ((olddir
& bitvector
) &&
321 !(dir
[number
] & bitvector
))
323 // The bit was set and now its now clear and
324 // we were interrupting on that bit before
325 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
326 DPRINTF(Tsunami
, "dim write resulting in clear"
327 " dir interrupt to cpu %d\n",
340 panic("TSDEV_CC_DIR write not implemented\n");
342 panic("TSDEV_CC_DRIR write not implemented\n");
344 panic("TSDEV_CC_PRBEN write not implemented\n");
349 panic("TSDEV_CC_IICx write not implemented\n");
354 panic("TSDEV_CC_MPRx write not implemented\n");
356 clearIPI(pkt
->get
<uint64_t>());
359 clearITI(pkt
->get
<uint64_t>());
362 reqIPI(pkt
->get
<uint64_t>());
365 panic("default in cchip read reached, accessing 0x%x\n");
367 } // not BIG_TSUNAMI write
368 pkt
->result
= Packet::Success
;
373 TsunamiCChip::clearIPI(uint64_t ipintr
)
375 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
376 assert(numcpus
<= Tsunami::Max_CPUs
);
379 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
380 // Check each cpu bit
381 uint64_t cpumask
= ULL(1) << cpunum
;
382 if (ipintr
& cpumask
) {
383 // Check if there is a pending ipi
384 if (ipint
& cpumask
) {
386 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
387 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
390 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
395 panic("Big IPI Clear, but not processors indicated\n");
399 TsunamiCChip::clearITI(uint64_t itintr
)
401 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
402 assert(numcpus
<= Tsunami::Max_CPUs
);
405 for (int i
=0; i
< numcpus
; i
++) {
406 uint64_t cpumask
= ULL(1) << i
;
407 if (itintr
& cpumask
& itint
) {
408 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
410 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
415 panic("Big ITI Clear, but not processors indicated\n");
419 TsunamiCChip::reqIPI(uint64_t ipreq
)
421 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
422 assert(numcpus
<= Tsunami::Max_CPUs
);
425 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
426 // Check each cpu bit
427 uint64_t cpumask
= ULL(1) << cpunum
;
428 if (ipreq
& cpumask
) {
429 // Check if there is already an ipi (bits 8:11)
430 if (!(ipint
& cpumask
)) {
432 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
433 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
436 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
441 panic("Big IPI Request, but not processors indicated\n");
446 TsunamiCChip::postRTC()
448 int size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
449 assert(size
<= Tsunami::Max_CPUs
);
451 for (int i
= 0; i
< size
; i
++) {
452 uint64_t cpumask
= ULL(1) << i
;
453 if (!(cpumask
& itint
)) {
455 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
456 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d", i
);
463 TsunamiCChip::postDRIR(uint32_t interrupt
)
465 uint64_t bitvector
= ULL(1) << interrupt
;
466 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
467 assert(size
<= Tsunami::Max_CPUs
);
470 for(int i
=0; i
< size
; i
++) {
471 dir
[i
] = dim
[i
] & drir
;
472 if (dim
[i
] & bitvector
) {
473 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
474 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
475 "interrupt %d\n",i
, interrupt
);
481 TsunamiCChip::clearDRIR(uint32_t interrupt
)
483 uint64_t bitvector
= ULL(1) << interrupt
;
484 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
485 assert(size
<= Tsunami::Max_CPUs
);
487 if (drir
& bitvector
)
490 for(int i
=0; i
< size
; i
++) {
491 if (dir
[i
] & bitvector
) {
492 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
493 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
494 "interrupt %d\n",i
, interrupt
);
497 dir
[i
] = dim
[i
] & drir
;
501 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
506 TsunamiCChip::serialize(std::ostream
&os
)
508 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
509 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
510 SERIALIZE_SCALAR(ipint
);
511 SERIALIZE_SCALAR(itint
);
512 SERIALIZE_SCALAR(drir
);
516 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
518 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
519 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
520 UNSERIALIZE_SCALAR(ipint
);
521 UNSERIALIZE_SCALAR(itint
);
522 UNSERIALIZE_SCALAR(drir
);
525 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
527 Param
<Addr
> pio_addr
;
528 Param
<Tick
> pio_latency
;
529 SimObjectParam
<Platform
*> platform
;
530 SimObjectParam
<System
*> system
;
531 SimObjectParam
<Tsunami
*> tsunami
;
533 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
535 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
537 INIT_PARAM(pio_addr
, "Device Address"),
538 INIT_PARAM(pio_latency
, "Programmed IO latency"),
539 INIT_PARAM(platform
, "platform"),
540 INIT_PARAM(system
, "system object"),
541 INIT_PARAM(tsunami
, "Tsunami")
543 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
545 CREATE_SIM_OBJECT(TsunamiCChip
)
547 TsunamiCChip::Params
*p
= new TsunamiCChip::Params
;
548 p
->name
= getInstanceName();
549 p
->pio_addr
= pio_addr
;
550 p
->pio_delay
= pio_latency
;
551 p
->platform
= platform
;
553 p
->tsunami
= tsunami
;
554 return new TsunamiCChip(p
);
557 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip
)