src/dev/alpha/tsunami_cchip.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  *          Ron Dreslinski
  30  */
  31
  32 /** @file
  33  * Emulation of the Tsunami CChip CSRs
  34  */
  35
  36 #include <deque>
  37 #include <string>
  38 #include <vector>
  39
  40 #include "arch/alpha/ev5.hh"
  41 #include "base/trace.hh"
  42 #include "cpu/intr_control.hh"
  43 #include "cpu/thread_context.hh"
  44 #include "dev/alpha/tsunami.hh"
  45 #include "dev/alpha/tsunami_cchip.hh"
  46 #include "dev/alpha/tsunamireg.h"
  47 #include "mem/packet.hh"
  48 #include "mem/packet_access.hh"
  49 #include "mem/port.hh"
  50 #include "params/TsunamiCChip.hh"
  51 #include "sim/system.hh"
  52
  53 using namespace std;
  54 //Should this be AlphaISA?
  55 using namespace TheISA;
  56
  57 TsunamiCChip::TsunamiCChip(const Params *p)
  58     : BasicPioDevice(p), tsunami(p->tsunami)
  59 {
  60     pioSize = 0x10000000;
  61
  62     drir = 0;
  63     ipint = 0;
  64     itint = 0;
  65
  66     for (int x = 0; x < Tsunami::Max_CPUs; x++)
  67     {
  68         dim[x] = 0;
  69         dir[x] = 0;
  70     }
  71
  72     //Put back pointer in tsunami
  73     tsunami->cchip = this;
  74 }
  75
  76 Tick
  77 TsunamiCChip::read(PacketPtr pkt)
  78 {
  79     DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
  80
  81     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  82
  83     Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
  84     Addr daddr = (pkt->getAddr() - pioAddr);
  85
  86     pkt->allocate();
  87     switch (pkt->getSize()) {
  88
  89       case sizeof(uint64_t):
  90           pkt->set<uint64_t>(0);
  91
  92           if (daddr & TSDEV_CC_BDIMS)
  93           {
  94               pkt->set(dim[(daddr >> 4) & 0x3F]);
  95               break;
  96           }
  97
  98           if (daddr & TSDEV_CC_BDIRS)
  99           {
 100               pkt->set(dir[(daddr >> 4) & 0x3F]);
 101               break;
 102           }
 103
 104           switch(regnum) {
 105               case TSDEV_CC_CSR:
 106                   pkt->set(0x0);
 107                   break;
 108               case TSDEV_CC_MTR:
 109                   panic("TSDEV_CC_MTR not implemeted\n");
 110                    break;
 111               case TSDEV_CC_MISC:
 112                   pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
 113                                      (pkt->req->getCpuNum() & 0x3));
 114                   break;
 115               case TSDEV_CC_AAR0:
 116               case TSDEV_CC_AAR1:
 117               case TSDEV_CC_AAR2:
 118               case TSDEV_CC_AAR3:
 119                   pkt->set(0);
 120                   break;
 121               case TSDEV_CC_DIM0:
 122                   pkt->set(dim[0]);
 123                   break;
 124               case TSDEV_CC_DIM1:
 125                   pkt->set(dim[1]);
 126                   break;
 127               case TSDEV_CC_DIM2:
 128                   pkt->set(dim[2]);
 129                   break;
 130               case TSDEV_CC_DIM3:
 131                   pkt->set(dim[3]);
 132                   break;
 133               case TSDEV_CC_DIR0:
 134                   pkt->set(dir[0]);
 135                   break;
 136               case TSDEV_CC_DIR1:
 137                   pkt->set(dir[1]);
 138                   break;
 139               case TSDEV_CC_DIR2:
 140                   pkt->set(dir[2]);
 141                   break;
 142               case TSDEV_CC_DIR3:
 143                   pkt->set(dir[3]);
 144                   break;
 145               case TSDEV_CC_DRIR:
 146                   pkt->set(drir);
 147                   break;
 148               case TSDEV_CC_PRBEN:
 149                   panic("TSDEV_CC_PRBEN not implemented\n");
 150                   break;
 151               case TSDEV_CC_IIC0:
 152               case TSDEV_CC_IIC1:
 153               case TSDEV_CC_IIC2:
 154               case TSDEV_CC_IIC3:
 155                   panic("TSDEV_CC_IICx not implemented\n");
 156                   break;
 157               case TSDEV_CC_MPR0:
 158               case TSDEV_CC_MPR1:
 159               case TSDEV_CC_MPR2:
 160               case TSDEV_CC_MPR3:
 161                   panic("TSDEV_CC_MPRx not implemented\n");
 162                   break;
 163               case TSDEV_CC_IPIR:
 164                   pkt->set(ipint);
 165                   break;
 166               case TSDEV_CC_ITIR:
 167                   pkt->set(itint);
 168                   break;
 169               default:
 170                   panic("default in cchip read reached, accessing 0x%x\n");
 171            } // uint64_t
 172
 173       break;
 174       case sizeof(uint32_t):
 175       case sizeof(uint16_t):
 176       case sizeof(uint8_t):
 177       default:
 178         panic("invalid access size(?) for tsunami register!\n");
 179     }
 180     DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
 181             regnum, pkt->getSize(), pkt->get<uint64_t>());
 182
 183     pkt->makeAtomicResponse();
 184     return pioDelay;
 185 }
 186
 187 Tick
 188 TsunamiCChip::write(PacketPtr pkt)
 189 {
 190     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 191     Addr daddr = pkt->getAddr() - pioAddr;
 192     Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
 193
 194
 195     assert(pkt->getSize() == sizeof(uint64_t));
 196
 197     DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
 198
 199     bool supportedWrite = false;
 200
 201
 202     if (daddr & TSDEV_CC_BDIMS)
 203     {
 204         int number = (daddr >> 4) & 0x3F;
 205
 206         uint64_t bitvector;
 207         uint64_t olddim;
 208         uint64_t olddir;
 209
 210         olddim = dim[number];
 211         olddir = dir[number];
 212         dim[number] = pkt->get<uint64_t>();
 213         dir[number] = dim[number] & drir;
 214         for(int x = 0; x < Tsunami::Max_CPUs; x++)
 215         {
 216             bitvector = ULL(1) << x;
 217             // Figure out which bits have changed
 218             if ((dim[number] & bitvector) != (olddim & bitvector))
 219             {
 220                 // The bit is now set and it wasn't before (set)
 221                 if((dim[number] & bitvector) && (dir[number] & bitvector))
 222                 {
 223                     tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 224                     DPRINTF(Tsunami, "dim write resulting in posting dir"
 225                             " interrupt to cpu %d\n", number);
 226                 }
 227                 else if ((olddir & bitvector) &&
 228                         !(dir[number] & bitvector))
 229                 {
 230                     // The bit was set and now its now clear and
 231                     // we were interrupting on that bit before
 232                     tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 233                     DPRINTF(Tsunami, "dim write resulting in clear"
 234                             " dir interrupt to cpu %d\n", number);
 235
 236                 }
 237
 238
 239             }
 240         }
 241     } else {
 242         switch(regnum) {
 243           case TSDEV_CC_CSR:
 244               panic("TSDEV_CC_CSR write\n");
 245           case TSDEV_CC_MTR:
 246               panic("TSDEV_CC_MTR write not implemented\n");
 247           case TSDEV_CC_MISC:
 248             uint64_t ipreq;
 249             ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
 250             //If it is bit 12-15, this is an IPI post
 251             if (ipreq) {
 252                 reqIPI(ipreq);
 253                 supportedWrite = true;
 254             }
 255
 256             //If it is bit 8-11, this is an IPI clear
 257             uint64_t ipintr;
 258             ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
 259             if (ipintr) {
 260                 clearIPI(ipintr);
 261                 supportedWrite = true;
 262             }
 263
 264             //If it is the 4-7th bit, clear the RTC interrupt
 265             uint64_t itintr;
 266               itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
 267             if (itintr) {
 268                   clearITI(itintr);
 269                 supportedWrite = true;
 270             }
 271
 272               // ignore NXMs
 273               if (pkt->get<uint64_t>() & 0x10000000)
 274                   supportedWrite = true;
 275
 276             if(!supportedWrite)
 277                   panic("TSDEV_CC_MISC write not implemented\n");
 278
 279             break;
 280             case TSDEV_CC_AAR0:
 281             case TSDEV_CC_AAR1:
 282             case TSDEV_CC_AAR2:
 283             case TSDEV_CC_AAR3:
 284                 panic("TSDEV_CC_AARx write not implemeted\n");
 285             case TSDEV_CC_DIM0:
 286             case TSDEV_CC_DIM1:
 287             case TSDEV_CC_DIM2:
 288             case TSDEV_CC_DIM3:
 289                 int number;
 290                 if(regnum == TSDEV_CC_DIM0)
 291                     number = 0;
 292                 else if(regnum == TSDEV_CC_DIM1)
 293                     number = 1;
 294                 else if(regnum == TSDEV_CC_DIM2)
 295                     number = 2;
 296                 else
 297                     number = 3;
 298
 299                 uint64_t bitvector;
 300                 uint64_t olddim;
 301                 uint64_t olddir;
 302
 303                 olddim = dim[number];
 304                 olddir = dir[number];
 305                 dim[number] = pkt->get<uint64_t>();
 306                 dir[number] = dim[number] & drir;
 307                 for(int x = 0; x < 64; x++)
 308                 {
 309                     bitvector = ULL(1) << x;
 310                     // Figure out which bits have changed
 311                     if ((dim[number] & bitvector) != (olddim & bitvector))
 312                     {
 313                         // The bit is now set and it wasn't before (set)
 314                         if((dim[number] & bitvector) && (dir[number] & bitvector))
 315                         {
 316                           tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 317                           DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
 318                         }
 319                         else if ((olddir & bitvector) &&
 320                                 !(dir[number] & bitvector))
 321                         {
 322                             // The bit was set and now its now clear and
 323                             // we were interrupting on that bit before
 324                             tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 325                           DPRINTF(Tsunami, "dim write resulting in clear"
 326                                     " dir interrupt to cpu %d\n",
 327                                     x);
 328
 329                         }
 330
 331
 332                     }
 333                 }
 334                 break;
 335             case TSDEV_CC_DIR0:
 336             case TSDEV_CC_DIR1:
 337             case TSDEV_CC_DIR2:
 338             case TSDEV_CC_DIR3:
 339                 panic("TSDEV_CC_DIR write not implemented\n");
 340             case TSDEV_CC_DRIR:
 341                 panic("TSDEV_CC_DRIR write not implemented\n");
 342             case TSDEV_CC_PRBEN:
 343                 panic("TSDEV_CC_PRBEN write not implemented\n");
 344             case TSDEV_CC_IIC0:
 345             case TSDEV_CC_IIC1:
 346             case TSDEV_CC_IIC2:
 347             case TSDEV_CC_IIC3:
 348                 panic("TSDEV_CC_IICx write not implemented\n");
 349             case TSDEV_CC_MPR0:
 350             case TSDEV_CC_MPR1:
 351             case TSDEV_CC_MPR2:
 352             case TSDEV_CC_MPR3:
 353                 panic("TSDEV_CC_MPRx write not implemented\n");
 354             case TSDEV_CC_IPIR:
 355                 clearIPI(pkt->get<uint64_t>());
 356                 break;
 357             case TSDEV_CC_ITIR:
 358                 clearITI(pkt->get<uint64_t>());
 359                 break;
 360             case TSDEV_CC_IPIQ:
 361                 reqIPI(pkt->get<uint64_t>());
 362                 break;
 363             default:
 364               panic("default in cchip read reached, accessing 0x%x\n");
 365         }  // swtich(regnum)
 366     } // not BIG_TSUNAMI write
 367     pkt->makeAtomicResponse();
 368     return pioDelay;
 369 }
 370
 371 void
 372 TsunamiCChip::clearIPI(uint64_t ipintr)
 373 {
 374     int numcpus = sys->threadContexts.size();
 375     assert(numcpus <= Tsunami::Max_CPUs);
 376
 377     if (ipintr) {
 378         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 379             // Check each cpu bit
 380             uint64_t cpumask = ULL(1) << cpunum;
 381             if (ipintr & cpumask) {
 382                 // Check if there is a pending ipi
 383                 if (ipint & cpumask) {
 384                     ipint &= ~cpumask;
 385                     tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 386                     DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
 387                 }
 388                 else
 389                     warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
 390             }
 391         }
 392     }
 393     else
 394         panic("Big IPI Clear, but not processors indicated\n");
 395 }
 396
 397 void
 398 TsunamiCChip::clearITI(uint64_t itintr)
 399 {
 400     int numcpus = sys->threadContexts.size();
 401     assert(numcpus <= Tsunami::Max_CPUs);
 402
 403     if (itintr) {
 404         for (int i=0; i < numcpus; i++) {
 405             uint64_t cpumask = ULL(1) << i;
 406             if (itintr & cpumask & itint) {
 407                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
 408                 itint &= ~cpumask;
 409                 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
 410             }
 411         }
 412     }
 413     else
 414         panic("Big ITI Clear, but not processors indicated\n");
 415 }
 416
 417 void
 418 TsunamiCChip::reqIPI(uint64_t ipreq)
 419 {
 420     int numcpus = sys->threadContexts.size();
 421     assert(numcpus <= Tsunami::Max_CPUs);
 422
 423     if (ipreq) {
 424         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 425             // Check each cpu bit
 426             uint64_t cpumask = ULL(1) << cpunum;
 427             if (ipreq & cpumask) {
 428                 // Check if there is already an ipi (bits 8:11)
 429                 if (!(ipint & cpumask)) {
 430                     ipint  |= cpumask;
 431                     tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 432                     DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
 433                 }
 434                 else
 435                     warn("post IPI for CPU=%d, but IPI already\n", cpunum);
 436             }
 437         }
 438     }
 439     else
 440         panic("Big IPI Request, but not processors indicated\n");
 441 }
 442
 443
 444 void
 445 TsunamiCChip::postRTC()
 446 {
 447     int size = sys->threadContexts.size();
 448     assert(size <= Tsunami::Max_CPUs);
 449
 450     for (int i = 0; i < size; i++) {
 451         uint64_t cpumask = ULL(1) << i;
 452        if (!(cpumask & itint)) {
 453            itint |= cpumask;
 454            tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
 455            DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
 456        }
 457     }
 458
 459 }
 460
 461 void
 462 TsunamiCChip::postDRIR(uint32_t interrupt)
 463 {
 464     uint64_t bitvector = ULL(1) << interrupt;
 465     uint64_t size = sys->threadContexts.size();
 466     assert(size <= Tsunami::Max_CPUs);
 467     drir |= bitvector;
 468
 469     for(int i=0; i < size; i++) {
 470         dir[i] = dim[i] & drir;
 471        if (dim[i] & bitvector) {
 472               tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
 473               DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
 474                         "interrupt %d\n",i, interrupt);
 475        }
 476     }
 477 }
 478
 479 void
 480 TsunamiCChip::clearDRIR(uint32_t interrupt)
 481 {
 482     uint64_t bitvector = ULL(1) << interrupt;
 483     uint64_t size = sys->threadContexts.size();
 484     assert(size <= Tsunami::Max_CPUs);
 485
 486     if (drir & bitvector)
 487     {
 488         drir &= ~bitvector;
 489         for(int i=0; i < size; i++) {
 490            if (dir[i] & bitvector) {
 491                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
 492                DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
 493                     "interrupt %d\n",i, interrupt);
 494
 495            }
 496            dir[i] = dim[i] & drir;
 497         }
 498     }
 499     else
 500         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 501 }
 502
 503
 504 void
 505 TsunamiCChip::serialize(std::ostream &os)
 506 {
 507     SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 508     SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 509     SERIALIZE_SCALAR(ipint);
 510     SERIALIZE_SCALAR(itint);
 511     SERIALIZE_SCALAR(drir);
 512 }
 513
 514 void
 515 TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
 516 {
 517     UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 518     UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 519     UNSERIALIZE_SCALAR(ipint);
 520     UNSERIALIZE_SCALAR(itint);
 521     UNSERIALIZE_SCALAR(drir);
 522 }
 523
 524 TsunamiCChip *
 525 TsunamiCChipParams::create()
 526 {
 527     return new TsunamiCChip(this);
 528 }