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32 * Emulation of the Tsunami CChip CSRs
35 #ifndef __TSUNAMI_CCHIP_HH__
36 #define __TSUNAMI_CCHIP_HH__
38 #include "dev/alpha/tsunami.hh"
39 #include "dev/io_device.hh"
40 #include "params/TsunamiCChip.hh"
43 * Tsunami CChip CSR Emulation. This device includes all the interrupt
44 * handling code for the chipset.
46 class TsunamiCChip : public BasicPioDevice
50 * pointer to the tsunami object.
51 * This is our access to all the other tsunami
57 * The dims are device interrupt mask registers.
58 * One exists for each CPU, the DRIR X DIM = DIR
60 uint64_t dim[Tsunami::Max_CPUs];
63 * The dirs are device interrupt registers.
64 * One exists for each CPU, the DRIR X DIM = DIR
66 uint64_t dir[Tsunami::Max_CPUs];
69 * This register contains bits for each PCI interrupt
74 /** Indicator of which CPUs have an IPI interrupt */
77 /** Indicator of which CPUs have an RTC interrupt */
81 typedef TsunamiCChipParams Params;
83 * Initialize the Tsunami CChip by setting all of the
84 * device register to 0.
85 * @param p params struct
87 TsunamiCChip(const Params *p);
92 return dynamic_cast<const Params *>(_params);
95 Tick read(PacketPtr pkt) override;
97 Tick write(PacketPtr pkt) override;
100 * post an RTC interrupt to the CPU
105 * post an interrupt to the CPU.
106 * @param interrupt the interrupt number to post (0-64)
108 void postDRIR(uint32_t interrupt);
111 * clear an interrupt previously posted to the CPU.
112 * @param interrupt the interrupt number to post (0-64)
114 void clearDRIR(uint32_t interrupt);
117 * post an ipi interrupt to the CPU.
118 * @param ipintr the cpu number to clear(bitvector)
120 void clearIPI(uint64_t ipintr);
123 * clear a timer interrupt previously posted to the CPU.
124 * @param itintr the cpu number to clear(bitvector)
126 void clearITI(uint64_t itintr);
129 * request an interrupt be posted to the CPU.
130 * @param ipreq the cpu number to interrupt(bitvector)
132 void reqIPI(uint64_t ipreq);
134 void serialize(CheckpointOut &cp) const override;
135 void unserialize(CheckpointIn &cp) override;
138 #endif // __TSUNAMI_CCHIP_HH__