fa4e697cf5169e4200aa863cd34bb02a608ebe2e
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Tsunami I/O including PIC, PIT, RTC, DMA
43 #include "base/time.hh"
44 #include "base/trace.hh"
45 #include "dev/rtcreg.h"
46 #include "dev/alpha/tsunami_cchip.hh"
47 #include "dev/alpha/tsunami.hh"
48 #include "dev/alpha/tsunami_io.hh"
49 #include "dev/alpha/tsunamireg.h"
50 #include "mem/packet.hh"
51 #include "mem/packet_access.hh"
52 #include "mem/port.hh"
53 #include "sim/system.hh"
56 //Should this be AlphaISA?
57 using namespace TheISA
;
59 TsunamiIO::TsunamiRTC::TsunamiRTC(const string
&n
, const TsunamiIOParams
*p
) :
60 MC146818(n
, p
->time
, p
->year_is_bcd
, p
->frequency
), tsunami(p
->tsunami
)
64 TsunamiIO::TsunamiIO(const Params
*p
)
65 : BasicPioDevice(p
), tsunami(p
->tsunami
), pitimer(p
->name
+ "pitimer"),
66 rtc(p
->name
+ ".rtc", p
)
70 // set the back pointer from tsunami to myself
75 picInterrupting
= false;
79 TsunamiIO::frequency() const
81 return Clock::Frequency
/ params()->frequency
;
85 TsunamiIO::read(PacketPtr pkt
)
87 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
89 Addr daddr
= pkt
->getAddr() - pioAddr
;
91 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n", pkt
->getAddr(),
92 pkt
->getSize(), daddr
);
96 if (pkt
->getSize() == sizeof(uint8_t)) {
102 case TSDEV_PIC2_MASK
:
106 // !!! If this is modified 64bit case needs to be too
107 // Pal code has to do a 64 bit physical read because there is
108 // no load physical byte instruction
112 // PIC2 not implemnted... just return 0
115 case TSDEV_TMR0_DATA
:
116 pkt
->set(pitimer
.counter0
.read());
118 case TSDEV_TMR1_DATA
:
119 pkt
->set(pitimer
.counter1
.read());
121 case TSDEV_TMR2_DATA
:
122 pkt
->set(pitimer
.counter2
.read());
125 pkt
->set(rtc
.readData(rtcAddr
));
127 case TSDEV_CTRL_PORTB
:
128 if (pitimer
.counter2
.outputHigh())
129 pkt
->set(PORTB_SPKR_HIGH
);
134 panic("I/O Read - va%#x size %d\n", pkt
->getAddr(), pkt
->getSize());
136 } else if (pkt
->getSize() == sizeof(uint64_t)) {
137 if (daddr
== TSDEV_PIC1_ISR
)
138 pkt
->set
<uint64_t>(picr
);
140 panic("I/O Read - invalid addr - va %#x size %d\n",
141 pkt
->getAddr(), pkt
->getSize());
143 panic("I/O Read - invalid size - va %#x size %d\n", pkt
->getAddr(), pkt
->getSize());
145 pkt
->makeAtomicResponse();
150 TsunamiIO::write(PacketPtr pkt
)
152 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
153 Addr daddr
= pkt
->getAddr() - pioAddr
;
155 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
156 pkt
->getAddr(), pkt
->getSize(), pkt
->getAddr() & 0xfff, (uint32_t)pkt
->get
<uint8_t>());
158 assert(pkt
->getSize() == sizeof(uint8_t));
161 case TSDEV_PIC1_MASK
:
162 mask1
= ~(pkt
->get
<uint8_t>());
163 if ((picr
& mask1
) && !picInterrupting
) {
164 picInterrupting
= true;
165 tsunami
->cchip
->postDRIR(55);
166 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
168 if ((!(picr
& mask1
)) && picInterrupting
) {
169 picInterrupting
= false;
170 tsunami
->cchip
->clearDRIR(55);
171 DPRINTF(Tsunami
, "clearing pic interrupt\n");
174 case TSDEV_PIC2_MASK
:
175 mask2
= pkt
->get
<uint8_t>();
176 //PIC2 Not implemented to interrupt
179 // clear the interrupt on the PIC
180 picr
&= ~(1 << (pkt
->get
<uint8_t>() & 0xF));
182 tsunami
->cchip
->clearDRIR(55);
184 case TSDEV_DMA1_MODE
:
185 mode1
= pkt
->get
<uint8_t>();
187 case TSDEV_DMA2_MODE
:
188 mode2
= pkt
->get
<uint8_t>();
190 case TSDEV_TMR0_DATA
:
191 pitimer
.counter0
.write(pkt
->get
<uint8_t>());
193 case TSDEV_TMR1_DATA
:
194 pitimer
.counter1
.write(pkt
->get
<uint8_t>());
196 case TSDEV_TMR2_DATA
:
197 pitimer
.counter2
.write(pkt
->get
<uint8_t>());
200 pitimer
.writeControl(pkt
->get
<uint8_t>());
203 rtcAddr
= pkt
->get
<uint8_t>();
206 rtc
.writeData(rtcAddr
, pkt
->get
<uint8_t>());
209 case TSDEV_DMA1_CMND
:
210 case TSDEV_DMA2_CMND
:
211 case TSDEV_DMA1_MMASK
:
212 case TSDEV_DMA2_MMASK
:
214 case TSDEV_DMA1_RESET
:
215 case TSDEV_DMA2_RESET
:
216 case TSDEV_DMA1_MASK
:
217 case TSDEV_DMA2_MASK
:
218 case TSDEV_CTRL_PORTB
:
221 panic("I/O Write - va%#x size %d data %#x\n", pkt
->getAddr(), pkt
->getSize(), pkt
->get
<uint8_t>());
224 pkt
->makeAtomicResponse();
229 TsunamiIO::postPIC(uint8_t bitvector
)
231 //PIC2 Is not implemented, because nothing of interest there
234 tsunami
->cchip
->postDRIR(55);
235 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
240 TsunamiIO::clearPIC(uint8_t bitvector
)
242 //PIC2 Is not implemented, because nothing of interest there
244 if (!(picr
& mask1
)) {
245 tsunami
->cchip
->clearDRIR(55);
246 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
251 TsunamiIO::serialize(ostream
&os
)
253 SERIALIZE_SCALAR(rtcAddr
);
254 SERIALIZE_SCALAR(timerData
);
255 SERIALIZE_SCALAR(mask1
);
256 SERIALIZE_SCALAR(mask2
);
257 SERIALIZE_SCALAR(mode1
);
258 SERIALIZE_SCALAR(mode2
);
259 SERIALIZE_SCALAR(picr
);
260 SERIALIZE_SCALAR(picInterrupting
);
262 // Serialize the timers
263 pitimer
.serialize("pitimer", os
);
264 rtc
.serialize("rtc", os
);
268 TsunamiIO::unserialize(Checkpoint
*cp
, const string
§ion
)
270 UNSERIALIZE_SCALAR(rtcAddr
);
271 UNSERIALIZE_SCALAR(timerData
);
272 UNSERIALIZE_SCALAR(mask1
);
273 UNSERIALIZE_SCALAR(mask2
);
274 UNSERIALIZE_SCALAR(mode1
);
275 UNSERIALIZE_SCALAR(mode2
);
276 UNSERIALIZE_SCALAR(picr
);
277 UNSERIALIZE_SCALAR(picInterrupting
);
279 // Unserialize the timers
280 pitimer
.unserialize("pitimer", cp
, section
);
281 rtc
.unserialize("rtc", cp
, section
);
285 TsunamiIOParams::create()
287 return new TsunamiIO(this);