2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Tsunami I/O including PIC, PIT, RTC, DMA
43 #include "base/trace.hh"
44 #include "dev/pitreg.h"
45 #include "dev/rtcreg.h"
46 #include "dev/alpha/tsunami_cchip.hh"
47 #include "dev/alpha/tsunami.hh"
48 #include "dev/alpha/tsunami_io.hh"
49 #include "dev/alpha/tsunamireg.h"
50 #include "mem/packet.hh"
51 #include "mem/packet_access.hh"
52 #include "mem/port.hh"
53 #include "sim/builder.hh"
54 #include "sim/system.hh"
57 //Should this be AlphaISA?
58 using namespace TheISA
;
60 TsunamiIO::RTC::RTC(const string
&name
, Tsunami
* t
, Tick i
)
61 : _name(name
), event(t
, i
), addr(0)
63 memset(clock_data
, 0, sizeof(clock_data
));
64 stat_regA
= RTCA_32768HZ
| RTCA_1024HZ
;
65 stat_regB
= RTCB_PRDC_IE
|RTCB_BIN
| RTCB_24HR
;
69 TsunamiIO::RTC::set_time(time_t t
)
77 wday
= tm
.tm_wday
+ 1;
82 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
86 TsunamiIO::RTC::writeAddr(const uint8_t data
)
88 if (data
<= RTC_STAT_REGD
)
91 panic("RTC addresses over 0xD are not implemented.\n");
95 TsunamiIO::RTC::writeData(const uint8_t data
)
97 if (addr
< RTC_STAT_REGA
)
98 clock_data
[addr
] = data
;
102 if (data
!= (RTCA_32768HZ
| RTCA_1024HZ
))
103 panic("Unimplemented RTC register A value write!\n");
107 if ((data
& ~(RTCB_PRDC_IE
| RTCB_SQWE
)) != (RTCB_BIN
| RTCB_24HR
))
108 panic("Write to RTC reg B bits that are not implemented!\n");
110 if (data
& RTCB_PRDC_IE
) {
111 if (!event
.scheduled())
112 event
.scheduleIntr();
114 if (event
.scheduled())
121 panic("RTC status registers C and D are not implemented.\n");
128 TsunamiIO::RTC::readData()
130 if (addr
< RTC_STAT_REGA
)
131 return clock_data
[addr
];
135 // toggle UIP bit for linux
136 stat_regA
^= RTCA_UIP
;
147 panic("Shouldn't be here");
153 TsunamiIO::RTC::serialize(const string
&base
, ostream
&os
)
155 paramOut(os
, base
+ ".addr", addr
);
156 arrayParamOut(os
, base
+ ".clock_data", clock_data
, sizeof(clock_data
));
157 paramOut(os
, base
+ ".stat_regA", stat_regA
);
158 paramOut(os
, base
+ ".stat_regB", stat_regB
);
162 TsunamiIO::RTC::unserialize(const string
&base
, Checkpoint
*cp
,
163 const string
§ion
)
165 paramIn(cp
, section
, base
+ ".addr", addr
);
166 arrayParamIn(cp
, section
, base
+ ".clock_data", clock_data
,
168 paramIn(cp
, section
, base
+ ".stat_regA", stat_regA
);
169 paramIn(cp
, section
, base
+ ".stat_regB", stat_regB
);
171 // We're not unserializing the event here, but we need to
172 // rescehedule the event since curTick was moved forward by the
174 event
.reschedule(curTick
+ event
.interval
);
177 TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami
*t
, Tick i
)
178 : Event(&mainEventQueue
), tsunami(t
), interval(i
)
180 DPRINTF(MC146818
, "RTC Event Initilizing\n");
181 schedule(curTick
+ interval
);
185 TsunamiIO::RTC::RTCEvent::scheduleIntr()
187 schedule(curTick
+ interval
);
191 TsunamiIO::RTC::RTCEvent::process()
193 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
194 schedule(curTick
+ interval
);
195 //Actually interrupt the processor here
196 tsunami
->cchip
->postRTC();
200 TsunamiIO::RTC::RTCEvent::description()
202 return "tsunami RTC interrupt";
205 TsunamiIO::PITimer::PITimer(const string
&name
)
206 : _name(name
), counter0(name
+ ".counter0"), counter1(name
+ ".counter1"),
207 counter2(name
+ ".counter2")
209 counter
[0] = &counter0
;
210 counter
[1] = &counter0
;
211 counter
[2] = &counter0
;
215 TsunamiIO::PITimer::writeControl(const uint8_t data
)
220 sel
= GET_CTRL_SEL(data
);
222 if (sel
== PIT_READ_BACK
)
223 panic("PITimer Read-Back Command is not implemented.\n");
225 rw
= GET_CTRL_RW(data
);
227 if (rw
== PIT_RW_LATCH_COMMAND
)
228 counter
[sel
]->latchCount();
230 counter
[sel
]->setRW(rw
);
231 counter
[sel
]->setMode(GET_CTRL_MODE(data
));
232 counter
[sel
]->setBCD(GET_CTRL_BCD(data
));
237 TsunamiIO::PITimer::serialize(const string
&base
, ostream
&os
)
239 // serialize the counters
240 counter0
.serialize(base
+ ".counter0", os
);
241 counter1
.serialize(base
+ ".counter1", os
);
242 counter2
.serialize(base
+ ".counter2", os
);
246 TsunamiIO::PITimer::unserialize(const string
&base
, Checkpoint
*cp
,
247 const string
§ion
)
249 // unserialze the counters
250 counter0
.unserialize(base
+ ".counter0", cp
, section
);
251 counter1
.unserialize(base
+ ".counter1", cp
, section
);
252 counter2
.unserialize(base
+ ".counter2", cp
, section
);
255 TsunamiIO::PITimer::Counter::Counter(const string
&name
)
256 : _name(name
), event(this), count(0), latched_count(0), period(0),
257 mode(0), output_high(false), latch_on(false), read_byte(LSB
),
264 TsunamiIO::PITimer::Counter::latchCount()
266 // behave like a real latch
270 latched_count
= count
;
275 TsunamiIO::PITimer::Counter::read()
281 return (uint8_t)latched_count
;
286 return latched_count
>> 8;
289 panic("Shouldn't be here");
295 return (uint8_t)count
;
302 panic("Shouldn't be here");
308 TsunamiIO::PITimer::Counter::write(const uint8_t data
)
310 switch (write_byte
) {
312 count
= (count
& 0xFF00) | data
;
314 if (event
.scheduled())
321 count
= (count
& 0x00FF) | (data
<< 8);
325 DPRINTF(Tsunami
, "Timer set to curTick + %d\n",
326 count
* event
.interval
);
327 event
.schedule(curTick
+ count
* event
.interval
);
335 TsunamiIO::PITimer::Counter::setRW(int rw_val
)
337 if (rw_val
!= PIT_RW_16BIT
)
338 panic("Only LSB/MSB read/write is implemented.\n");
342 TsunamiIO::PITimer::Counter::setMode(int mode_val
)
344 if(mode_val
!= PIT_MODE_INTTC
&& mode_val
!= PIT_MODE_RATEGEN
&&
345 mode_val
!= PIT_MODE_SQWAVE
)
346 panic("PIT mode %#x is not implemented: \n", mode_val
);
352 TsunamiIO::PITimer::Counter::setBCD(int bcd_val
)
354 if (bcd_val
!= PIT_BCD_FALSE
)
355 panic("PITimer does not implement BCD counts.\n");
359 TsunamiIO::PITimer::Counter::outputHigh()
365 TsunamiIO::PITimer::Counter::serialize(const string
&base
, ostream
&os
)
367 paramOut(os
, base
+ ".count", count
);
368 paramOut(os
, base
+ ".latched_count", latched_count
);
369 paramOut(os
, base
+ ".period", period
);
370 paramOut(os
, base
+ ".mode", mode
);
371 paramOut(os
, base
+ ".output_high", output_high
);
372 paramOut(os
, base
+ ".latch_on", latch_on
);
373 paramOut(os
, base
+ ".read_byte", read_byte
);
374 paramOut(os
, base
+ ".write_byte", write_byte
);
377 if (event
.scheduled())
378 event_tick
= event
.when();
379 paramOut(os
, base
+ ".event_tick", event_tick
);
383 TsunamiIO::PITimer::Counter::unserialize(const string
&base
, Checkpoint
*cp
,
384 const string
§ion
)
386 paramIn(cp
, section
, base
+ ".count", count
);
387 paramIn(cp
, section
, base
+ ".latched_count", latched_count
);
388 paramIn(cp
, section
, base
+ ".period", period
);
389 paramIn(cp
, section
, base
+ ".mode", mode
);
390 paramIn(cp
, section
, base
+ ".output_high", output_high
);
391 paramIn(cp
, section
, base
+ ".latch_on", latch_on
);
392 paramIn(cp
, section
, base
+ ".read_byte", read_byte
);
393 paramIn(cp
, section
, base
+ ".write_byte", write_byte
);
396 paramIn(cp
, section
, base
+ ".event_tick", event_tick
);
398 event
.schedule(event_tick
);
401 TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter
* c_ptr
)
402 : Event(&mainEventQueue
)
404 interval
= (Tick
)(Clock::Float::s
/ 1193180.0);
409 TsunamiIO::PITimer::Counter::CounterEvent::process()
411 DPRINTF(Tsunami
, "Timer Interrupt\n");
412 switch (counter
->mode
) {
414 counter
->output_high
= true;
415 case PIT_MODE_RATEGEN
:
416 case PIT_MODE_SQWAVE
:
419 panic("Unimplemented PITimer mode.\n");
424 TsunamiIO::PITimer::Counter::CounterEvent::description()
426 return "tsunami 8254 Interval timer";
429 TsunamiIO::TsunamiIO(Params
*p
)
430 : BasicPioDevice(p
), tsunami(p
->tsunami
), pitimer(p
->name
+ "pitimer"),
431 rtc(p
->name
+ ".rtc", p
->tsunami
, p
->frequency
)
435 // set the back pointer from tsunami to myself
439 rtc
.set_time(p
->init_time
== 0 ? time(NULL
) : p
->init_time
);
441 picInterrupting
= false;
445 TsunamiIO::frequency() const
447 return Clock::Frequency
/ params()->frequency
;
451 TsunamiIO::read(PacketPtr pkt
)
453 assert(pkt
->result
== Packet::Unknown
);
454 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
456 Addr daddr
= pkt
->getAddr() - pioAddr
;
458 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n", pkt
->getAddr(),
459 pkt
->getSize(), daddr
);
463 if (pkt
->getSize() == sizeof(uint8_t)) {
466 case TSDEV_PIC1_MASK
:
469 case TSDEV_PIC2_MASK
:
473 // !!! If this is modified 64bit case needs to be too
474 // Pal code has to do a 64 bit physical read because there is
475 // no load physical byte instruction
479 // PIC2 not implemnted... just return 0
482 case TSDEV_TMR0_DATA
:
483 pkt
->set(pitimer
.counter0
.read());
485 case TSDEV_TMR1_DATA
:
486 pkt
->set(pitimer
.counter1
.read());
488 case TSDEV_TMR2_DATA
:
489 pkt
->set(pitimer
.counter2
.read());
492 pkt
->set(rtc
.readData());
494 case TSDEV_CTRL_PORTB
:
495 if (pitimer
.counter2
.outputHigh())
496 pkt
->set(PORTB_SPKR_HIGH
);
501 panic("I/O Read - va%#x size %d\n", pkt
->getAddr(), pkt
->getSize());
503 } else if (pkt
->getSize() == sizeof(uint64_t)) {
504 if (daddr
== TSDEV_PIC1_ISR
)
505 pkt
->set
<uint64_t>(picr
);
507 panic("I/O Read - invalid addr - va %#x size %d\n",
508 pkt
->getAddr(), pkt
->getSize());
510 panic("I/O Read - invalid size - va %#x size %d\n", pkt
->getAddr(), pkt
->getSize());
512 pkt
->result
= Packet::Success
;
517 TsunamiIO::write(PacketPtr pkt
)
519 assert(pkt
->result
== Packet::Unknown
);
520 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
521 Addr daddr
= pkt
->getAddr() - pioAddr
;
523 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
524 pkt
->getAddr(), pkt
->getSize(), pkt
->getAddr() & 0xfff, (uint32_t)pkt
->get
<uint8_t>());
526 assert(pkt
->getSize() == sizeof(uint8_t));
529 case TSDEV_PIC1_MASK
:
530 mask1
= ~(pkt
->get
<uint8_t>());
531 if ((picr
& mask1
) && !picInterrupting
) {
532 picInterrupting
= true;
533 tsunami
->cchip
->postDRIR(55);
534 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
536 if ((!(picr
& mask1
)) && picInterrupting
) {
537 picInterrupting
= false;
538 tsunami
->cchip
->clearDRIR(55);
539 DPRINTF(Tsunami
, "clearing pic interrupt\n");
542 case TSDEV_PIC2_MASK
:
543 mask2
= pkt
->get
<uint8_t>();
544 //PIC2 Not implemented to interrupt
547 // clear the interrupt on the PIC
548 picr
&= ~(1 << (pkt
->get
<uint8_t>() & 0xF));
550 tsunami
->cchip
->clearDRIR(55);
552 case TSDEV_DMA1_MODE
:
553 mode1
= pkt
->get
<uint8_t>();
555 case TSDEV_DMA2_MODE
:
556 mode2
= pkt
->get
<uint8_t>();
558 case TSDEV_TMR0_DATA
:
559 pitimer
.counter0
.write(pkt
->get
<uint8_t>());
561 case TSDEV_TMR1_DATA
:
562 pitimer
.counter1
.write(pkt
->get
<uint8_t>());
564 case TSDEV_TMR2_DATA
:
565 pitimer
.counter2
.write(pkt
->get
<uint8_t>());
568 pitimer
.writeControl(pkt
->get
<uint8_t>());
571 rtc
.writeAddr(pkt
->get
<uint8_t>());
574 rtc
.writeData(pkt
->get
<uint8_t>());
577 case TSDEV_DMA1_CMND
:
578 case TSDEV_DMA2_CMND
:
579 case TSDEV_DMA1_MMASK
:
580 case TSDEV_DMA2_MMASK
:
582 case TSDEV_DMA1_RESET
:
583 case TSDEV_DMA2_RESET
:
584 case TSDEV_DMA1_MASK
:
585 case TSDEV_DMA2_MASK
:
586 case TSDEV_CTRL_PORTB
:
589 panic("I/O Write - va%#x size %d data %#x\n", pkt
->getAddr(), pkt
->getSize(), pkt
->get
<uint8_t>());
592 pkt
->result
= Packet::Success
;
597 TsunamiIO::postPIC(uint8_t bitvector
)
599 //PIC2 Is not implemented, because nothing of interest there
602 tsunami
->cchip
->postDRIR(55);
603 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
608 TsunamiIO::clearPIC(uint8_t bitvector
)
610 //PIC2 Is not implemented, because nothing of interest there
612 if (!(picr
& mask1
)) {
613 tsunami
->cchip
->clearDRIR(55);
614 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
619 TsunamiIO::serialize(ostream
&os
)
621 SERIALIZE_SCALAR(timerData
);
622 SERIALIZE_SCALAR(mask1
);
623 SERIALIZE_SCALAR(mask2
);
624 SERIALIZE_SCALAR(mode1
);
625 SERIALIZE_SCALAR(mode2
);
626 SERIALIZE_SCALAR(picr
);
627 SERIALIZE_SCALAR(picInterrupting
);
629 // Serialize the timers
630 pitimer
.serialize("pitimer", os
);
631 rtc
.serialize("rtc", os
);
635 TsunamiIO::unserialize(Checkpoint
*cp
, const string
§ion
)
637 UNSERIALIZE_SCALAR(timerData
);
638 UNSERIALIZE_SCALAR(mask1
);
639 UNSERIALIZE_SCALAR(mask2
);
640 UNSERIALIZE_SCALAR(mode1
);
641 UNSERIALIZE_SCALAR(mode2
);
642 UNSERIALIZE_SCALAR(picr
);
643 UNSERIALIZE_SCALAR(picInterrupting
);
645 // Unserialize the timers
646 pitimer
.unserialize("pitimer", cp
, section
);
647 rtc
.unserialize("rtc", cp
, section
);
650 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
652 Param
<Addr
> pio_addr
;
653 Param
<Tick
> pio_latency
;
654 Param
<Tick
> frequency
;
655 SimObjectParam
<Platform
*> platform
;
656 SimObjectParam
<System
*> system
;
658 SimObjectParam
<Tsunami
*> tsunami
;
660 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
662 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
664 INIT_PARAM(pio_addr
, "Device Address"),
665 INIT_PARAM(pio_latency
, "Programmed IO latency"),
666 INIT_PARAM(frequency
, "clock interrupt frequency"),
667 INIT_PARAM(platform
, "platform"),
668 INIT_PARAM(system
, "system object"),
669 INIT_PARAM(time
, "System time to use (0 for actual time"),
670 INIT_PARAM(tsunami
, "Tsunami")
672 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
674 CREATE_SIM_OBJECT(TsunamiIO
)
676 TsunamiIO::Params
*p
= new TsunamiIO::Params
;
677 p
->frequency
= frequency
;
678 p
->name
= getInstanceName();
679 p
->pio_addr
= pio_addr
;
680 p
->pio_delay
= pio_latency
;
681 p
->platform
= platform
;
684 p
->tsunami
= tsunami
;
685 return new TsunamiIO(p
);
688 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO
)