2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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40 #include "base/trace.hh"
41 #include "config/the_isa.hh"
42 #include "debug/Tsunami.hh"
43 #include "dev/alpha/tsunami.hh"
44 #include "dev/alpha/tsunami_pchip.hh"
45 #include "dev/alpha/tsunamireg.h"
46 #include "mem/packet.hh"
47 #include "mem/packet_access.hh"
48 #include "sim/system.hh"
51 //Should this be AlphaISA?
52 using namespace TheISA
;
54 TsunamiPChip::TsunamiPChip(const Params
*p
)
59 for (int i
= 0; i
< 4; i
++) {
65 // initialize pchip control register
66 pctl
= (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
68 //Set back pointer in tsunami
69 p
->tsunami
->pchip
= this;
73 TsunamiPChip::read(PacketPtr pkt
)
75 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
78 Addr daddr
= (pkt
->getAddr() - pioAddr
) >> 6;;
79 assert(pkt
->getSize() == sizeof(uint64_t));
82 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
125 panic("PC_PLAT not implemented\n");
127 panic("PC_RES not implemented\n");
128 case TSDEV_PC_PERROR
:
129 pkt
->set((uint64_t)0x00);
131 case TSDEV_PC_PERRMASK
:
132 pkt
->set((uint64_t)0x00);
134 case TSDEV_PC_PERRSET
:
135 panic("PC_PERRSET not implemented\n");
137 panic("PC_TLBIV not implemented\n");
139 pkt
->set((uint64_t)0x00); // shouldn't be readable, but linux
141 case TSDEV_PC_PMONCTL
:
142 panic("PC_PMONCTL not implemented\n");
143 case TSDEV_PC_PMONCNT
:
144 panic("PC_PMONCTN not implemented\n");
146 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
148 pkt
->makeAtomicResponse();
154 TsunamiPChip::write(PacketPtr pkt
)
156 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
157 Addr daddr
= (pkt
->getAddr() - pioAddr
) >> 6;
159 assert(pkt
->getSize() == sizeof(uint64_t));
161 DPRINTF(Tsunami
, "write - va=%#x size=%d \n", pkt
->getAddr(), pkt
->getSize());
165 wsba
[0] = pkt
->get
<uint64_t>();
168 wsba
[1] = pkt
->get
<uint64_t>();
171 wsba
[2] = pkt
->get
<uint64_t>();
174 wsba
[3] = pkt
->get
<uint64_t>();
177 wsm
[0] = pkt
->get
<uint64_t>();
180 wsm
[1] = pkt
->get
<uint64_t>();
183 wsm
[2] = pkt
->get
<uint64_t>();
186 wsm
[3] = pkt
->get
<uint64_t>();
189 tba
[0] = pkt
->get
<uint64_t>();
192 tba
[1] = pkt
->get
<uint64_t>();
195 tba
[2] = pkt
->get
<uint64_t>();
198 tba
[3] = pkt
->get
<uint64_t>();
201 pctl
= pkt
->get
<uint64_t>();
204 panic("PC_PLAT not implemented\n");
206 panic("PC_RES not implemented\n");
207 case TSDEV_PC_PERROR
:
209 case TSDEV_PC_PERRMASK
:
210 panic("PC_PERRMASK not implemented\n");
211 case TSDEV_PC_PERRSET
:
212 panic("PC_PERRSET not implemented\n");
214 panic("PC_TLBIV not implemented\n");
216 break; // value ignored, supposted to invalidate SG TLB
217 case TSDEV_PC_PMONCTL
:
218 panic("PC_PMONCTL not implemented\n");
219 case TSDEV_PC_PMONCNT
:
220 panic("PC_PMONCTN not implemented\n");
222 panic("Default in PChip write reached reading 0x%x\n", daddr
);
226 pkt
->makeAtomicResponse();
230 #define DMA_ADDR_MASK ULL(0x3ffffffff)
233 TsunamiPChip::translatePciToDma(Addr busAddr
)
235 // compare the address to the window base registers
236 uint64_t tbaMask
= 0;
239 uint64_t windowMask
= 0;
240 uint64_t windowBase
= 0;
242 uint64_t pteEntry
= 0;
248 DPRINTF(IdeDisk
, "Translation for bus address: %#x\n", busAddr
);
249 for (int i
= 0; i
< 4; i
++) {
250 DPRINTF(IdeDisk
, "(%d) base:%#x mask:%#x\n",
253 windowBase
= wsba
[i
];
254 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
256 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
257 DPRINTF(IdeDisk
, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
258 i
, windowBase
, windowMask
, (busAddr
& windowMask
),
259 (windowBase
& windowMask
));
264 for (int i
= 0; i
< 4; i
++) {
266 windowBase
= wsba
[i
];
267 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
269 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
271 if (wsba
[i
] & 0x1) { // see if enabled
272 if (wsba
[i
] & 0x2) { // see if SG bit is set
274 This currently is faked by just doing a direct
275 read from memory, however, to be realistic, this
276 needs to actually do a bus transaction. The process
277 is explained in the tsunami documentation on page
278 10-12 and basically munges the address to look up a
279 PTE from a table in memory and then uses that mapping
280 to create an address for the SG page
283 tbaMask
= ~(((wsm
[i
] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
284 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
285 pteAddr
= (tba
[i
] & tbaMask
) | ((busAddr
& baMask
) >> 10);
287 sys
->physProxy
.readBlob(pteAddr
, (uint8_t*)&pteEntry
,
290 dmaAddr
= ((pteEntry
& ~ULL(0x1)) << 12) | (busAddr
& ULL(0x1fff));
293 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | ULL(0xfffff);
295 dmaAddr
= (tba
[i
] & tbaMask
) | (busAddr
& baMask
);
298 return (dmaAddr
& DMA_ADDR_MASK
);
303 // if no match was found, then return the original address
308 TsunamiPChip::calcConfigAddr(int bus
, int dev
, int func
)
314 return TsunamiPciBus0Config
| (func
<< 8) | (dev
<< 11);
318 TsunamiPChip::calcIOAddr(Addr addr
)
320 return TSUNAMI_PCI0_IO
+ addr
;
324 TsunamiPChip::calcMemAddr(Addr addr
)
326 return TSUNAMI_PCI0_MEMORY
+ addr
;
330 TsunamiPChip::serialize(std::ostream
&os
)
332 SERIALIZE_SCALAR(pctl
);
333 SERIALIZE_ARRAY(wsba
, 4);
334 SERIALIZE_ARRAY(wsm
, 4);
335 SERIALIZE_ARRAY(tba
, 4);
339 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
341 UNSERIALIZE_SCALAR(pctl
);
342 UNSERIALIZE_ARRAY(wsba
, 4);
343 UNSERIALIZE_ARRAY(wsm
, 4);
344 UNSERIALIZE_ARRAY(tba
, 4);
349 TsunamiPChipParams::create()
351 return new TsunamiPChip(this);