src/dev/arm/Gic.py

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  35
  36 from m5.params import *
  37 from m5.proxy import *
  38 from m5.util.fdthelper import *
  39 from m5.SimObject import SimObject
  40
  41 from m5.objects.Device import PioDevice, BasicPioDevice
  42 from m5.objects.Platform import Platform
  43
  44 class BaseGic(PioDevice):
  45     type = 'BaseGic'
  46     abstract = True
  47     cxx_header = "dev/arm/base_gic.hh"
  48
  49     # Used for DTB autogeneration
  50     _state = FdtState(addr_cells=0, interrupt_cells=3)
  51
  52     platform = Param.Platform(Parent.any, "Platform this device is part of.")
  53
  54     gicd_iidr = Param.UInt32(0,
  55         "Distributor Implementer Identification Register")
  56     gicd_pidr = Param.UInt32(0,
  57         "Peripheral Identification Register")
  58     gicc_iidr = Param.UInt32(0,
  59         "CPU Interface Identification Register")
  60     gicv_iidr = Param.UInt32(0,
  61         "VM CPU Interface Identification Register")
  62
  63     def interruptCells(self, int_type, int_num, int_flag):
  64         """
  65         Interupt cells generation helper:
  66         Following specifications described in
  67
  68         Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
  69         """
  70         assert self._state.interrupt_cells == 3
  71         return [ int_type, int_num, int_flag ]
  72
  73 class ArmInterruptPin(SimObject):
  74     type = 'ArmInterruptPin'
  75     cxx_header = "dev/arm/base_gic.hh"
  76     cxx_class = "ArmInterruptPinGen"
  77     abstract = True
  78
  79     platform = Param.Platform(Parent.any, "Platform with interrupt controller")
  80     num = Param.UInt32("Interrupt number in GIC")
  81
  82 class ArmSPI(ArmInterruptPin):
  83     type = 'ArmSPI'
  84     cxx_header = "dev/arm/base_gic.hh"
  85     cxx_class = "ArmSPIGen"
  86
  87 class ArmPPI(ArmInterruptPin):
  88     type = 'ArmPPI'
  89     cxx_header = "dev/arm/base_gic.hh"
  90     cxx_class = "ArmPPIGen"
  91
  92 class GicV2(BaseGic):
  93     type = 'GicV2'
  94     cxx_header = "dev/arm/gic_v2.hh"
  95
  96     dist_addr = Param.Addr("Address for distributor")
  97     cpu_addr = Param.Addr("Address for cpu")
  98     cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
  99     dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
 100     cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
 101     int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
 102     it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
 103     gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
 104
 105 class Gic400(GicV2):
 106     """
 107     As defined in:
 108     "ARM Generic Interrupt Controller Architecture" version 2.0
 109     "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
 110     """
 111     gicd_pidr = 0x002bb490
 112     gicd_iidr = 0x0200143B
 113     gicc_iidr = 0x0202143B
 114
 115     # gicv_iidr same as gicc_idr
 116     gicv_iidr = gicc_iidr
 117
 118 class Gicv2mFrame(SimObject):
 119     type = 'Gicv2mFrame'
 120     cxx_header = "dev/arm/gic_v2m.hh"
 121     spi_base = Param.UInt32(0x0, "Frame SPI base number");
 122     spi_len = Param.UInt32(0x0, "Frame SPI total number");
 123     addr = Param.Addr("Address for frame PIO")
 124
 125 class Gicv2m(PioDevice):
 126     type = 'Gicv2m'
 127     cxx_header = "dev/arm/gic_v2m.hh"
 128
 129     pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
 130     gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
 131     frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
 132
 133 class VGic(PioDevice):
 134     type = 'VGic'
 135     cxx_header = "dev/arm/vgic.hh"
 136     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
 137     platform = Param.Platform(Parent.any, "Platform this device is part of.")
 138     vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
 139     hv_addr = Param.Addr(0, "Address for hv control")
 140     pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
 141    # The number of list registers is not currently configurable at runtime.
 142     maint_int = Param.UInt32("HV maintenance interrupt number")
 143
 144     # gicv_iidr same as gicc_idr
 145     gicv_iidr = Param.UInt32(Self.gic.gicc_iidr,
 146         "VM CPU Interface Identification Register")
 147
 148     def generateDeviceTree(self, state):
 149         gic = self.gic.unproxy(self)
 150
 151         node = FdtNode("interrupt-controller")
 152         node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
 153                                "arm,cortex-a9-gic"])
 154         node.append(gic._state.interruptCellsProperty())
 155         node.append(gic._state.addrCellsProperty())
 156         node.append(FdtProperty("interrupt-controller"))
 157
 158         regs = (
 159             state.addrCells(gic.dist_addr) +
 160             state.sizeCells(0x1000) +
 161             state.addrCells(gic.cpu_addr) +
 162             state.sizeCells(0x1000) +
 163             state.addrCells(self.hv_addr) +
 164             state.sizeCells(0x2000) +
 165             state.addrCells(self.vcpu_addr) +
 166             state.sizeCells(0x2000) )
 167
 168         node.append(FdtPropertyWords("reg", regs))
 169         node.append(FdtPropertyWords("interrupts",
 170                                      [1, int(self.maint_int)-16, 0xf04]))
 171
 172         node.appendPhandle(gic)
 173
 174         yield node
 175
 176 class Gicv3Its(BasicPioDevice):
 177     type = 'Gicv3Its'
 178     cxx_header = "dev/arm/gic_v3_its.hh"
 179
 180     dma = MasterPort("DMA port")
 181     pio_size = Param.Unsigned(0x20000, "Gicv3Its pio size")
 182
 183     # CIL [36] = 0: ITS supports 16-bit CollectionID
 184     # Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits
 185     # ID_bits [12:8] = 0b11111: ITS supports 31 EventID bits
 186     gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value")
 187
 188     def generateDeviceTree(self, state):
 189         node = self.generateBasicPioDeviceNode(state, "gic-its", self.pio_addr,
 190                                                self.pio_size)
 191         node.appendCompatible(["arm,gic-v3-its"])
 192         node.append(FdtProperty("msi-controller"))
 193         node.append(FdtPropertyWords("#msi-cells", [1]))
 194
 195         return node
 196
 197 class Gicv3(BaseGic):
 198     type = 'Gicv3'
 199     cxx_header = "dev/arm/gic_v3.hh"
 200
 201     # Used for DTB autogeneration
 202     _state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
 203
 204     its = Param.Gicv3Its(NULL, "GICv3 Interrupt Translation Service")
 205
 206     dist_addr = Param.Addr("Address for distributor")
 207     dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
 208     redist_addr = Param.Addr("Address for redistributors")
 209     redist_pio_delay = Param.Latency('10ns',
 210             "Delay for PIO r/w to redistributors")
 211     it_lines = Param.UInt32(1020,
 212             "Number of interrupt lines supported (max = 1020)")
 213
 214     maint_int = Param.ArmInterruptPin(
 215         "HV maintenance interrupt."
 216         "ARM strongly recommends that maintenance interrupts "
 217         "are configured to use INTID 25 (PPI Interrupt).")
 218
 219     cpu_max = Param.Unsigned(256,
 220         "Maximum number of PE. This is affecting the maximum number of "
 221         "redistributors")
 222
 223     gicv4 = Param.Bool(True, "GICv4 extension available")
 224
 225     def interruptCells(self, int_type, int_num, int_flag):
 226         """
 227         Interupt cells generation helper:
 228         Following specifications described in
 229
 230         Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
 231         """
 232         prop = self._state.interruptCells(0)
 233         assert len(prop) >= 3
 234         prop[0] = int_type
 235         prop[1] = int_num
 236         prop[2] = int_flag
 237         return prop
 238
 239     def generateDeviceTree(self, state):
 240         node = FdtNode("interrupt-controller")
 241         node.appendCompatible(["arm,gic-v3"])
 242         node.append(self._state.interruptCellsProperty())
 243         node.append(self._state.addrCellsProperty())
 244         node.append(self._state.sizeCellsProperty())
 245         node.append(FdtProperty("ranges"))
 246         node.append(FdtProperty("interrupt-controller"))
 247
 248         redist_stride = 0x40000 if self.gicv4 else 0x20000
 249         node.append(FdtPropertyWords("redistributor-stride",
 250             state.sizeCells(redist_stride)))
 251
 252         regs = (
 253             state.addrCells(self.dist_addr) +
 254             state.sizeCells(0x10000) +
 255             state.addrCells(self.redist_addr) +
 256             state.sizeCells(0x2000000) )
 257
 258         node.append(FdtPropertyWords("reg", regs))
 259         node.append(FdtPropertyWords("interrupts",
 260             self.interruptCells(1, int(self.maint_int.num)-16, 0xf04)))
 261
 262         node.appendPhandle(self)
 263
 264         # Generate the ITS device tree if instantiated
 265         if self.its != NULL:
 266             node.append(self.its.generateDeviceTree(self._state))
 267
 268         yield node