1 # Copyright (c) 2009-2015 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 from m5
.params
import *
44 from m5
.proxy
import *
45 from ClockDomain
import ClockDomain
46 from VoltageDomain
import VoltageDomain
47 from Device
import BasicPioDevice
, PioDevice
, IsaFake
, BadAddr
, DmaDevice
49 from Ethernet
import NSGigE
, IGbE_igb
, IGbE_e1000
51 from Platform
import Platform
52 from Terminal
import Terminal
54 from SimpleMemory
import SimpleMemory
56 from EnergyCtrl
import EnergyCtrl
57 from ClockDomain
import SrcClockDomain
58 from SubSystem
import SubSystem
60 class AmbaPioDevice(BasicPioDevice
):
61 type = 'AmbaPioDevice'
63 cxx_header
= "dev/arm/amba_device.hh"
64 amba_id
= Param
.UInt32("ID of AMBA device for kernel detection")
66 class AmbaIntDevice(AmbaPioDevice
):
67 type = 'AmbaIntDevice'
69 cxx_header
= "dev/arm/amba_device.hh"
70 gic
= Param
.BaseGic(Parent
.any
, "Gic to use for interrupting")
71 int_num
= Param
.UInt32("Interrupt number that connects to GIC")
72 int_delay
= Param
.Latency("100ns",
73 "Time between action and interrupt generation by device")
75 class AmbaDmaDevice(DmaDevice
):
76 type = 'AmbaDmaDevice'
78 cxx_header
= "dev/arm/amba_device.hh"
79 pio_addr
= Param
.Addr("Address for AMBA slave interface")
80 pio_latency
= Param
.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
81 gic
= Param
.BaseGic(Parent
.any
, "Gic to use for interrupting")
82 int_num
= Param
.UInt32("Interrupt number that connects to GIC")
83 amba_id
= Param
.UInt32("ID of AMBA device for kernel detection")
85 class A9SCU(BasicPioDevice
):
87 cxx_header
= "dev/arm/a9scu.hh"
89 class ArmPciIntRouting(Enum
): vals
= [
95 class GenericArmPciHost(GenericPciHost
):
96 type = 'GenericArmPciHost'
97 cxx_header
= "dev/arm/pci_host.hh"
99 int_policy
= Param
.ArmPciIntRouting("PCI interrupt routing policy")
100 int_base
= Param
.Unsigned("PCI interrupt base")
101 int_count
= Param
.Unsigned("Maximum number of interrupts used by this host")
103 class RealViewCtrl(BasicPioDevice
):
104 type = 'RealViewCtrl'
105 cxx_header
= "dev/arm/rv_ctrl.hh"
106 proc_id0
= Param
.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
107 proc_id1
= Param
.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
108 idreg
= Param
.UInt32(0x00000000, "ID Register, SYS_ID")
110 class RealViewOsc(ClockDomain
):
112 cxx_header
= "dev/arm/rv_ctrl.hh"
114 parent
= Param
.RealViewCtrl(Parent
.any
, "RealView controller")
116 # TODO: We currently don't have the notion of a clock source,
117 # which means we have to associate oscillators with a voltage
119 voltage_domain
= Param
.VoltageDomain(Parent
.voltage_domain
,
122 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
123 # the individual core/logic tile reference manuals for details
124 # about the site/position/dcc/device allocation.
125 site
= Param
.UInt8("Board Site")
126 position
= Param
.UInt8("Position in device stack")
127 dcc
= Param
.UInt8("Daughterboard Configuration Controller")
128 device
= Param
.UInt8("Device ID")
130 freq
= Param
.Clock("Default frequency")
132 class VExpressMCC(SubSystem
):
133 """ARM V2M-P1 Motherboard Configuration Controller
135 This subsystem describes a subset of the devices that sit behind the
136 motherboard configuration controller on the the ARM Motherboard
137 Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
140 class Osc(RealViewOsc
):
141 site
, position
, dcc
= (0, 0, 0)
143 osc_mcc
= Osc(device
=0, freq
="50MHz")
144 osc_clcd
= Osc(device
=1, freq
="23.75MHz")
145 osc_peripheral
= Osc(device
=2, freq
="24MHz")
146 osc_system_bus
= Osc(device
=4, freq
="24MHz")
148 class CoreTile2A15DCC(SubSystem
):
149 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
151 This subsystem describes a subset of the devices that sit behind the
152 daughterboard configuration controller on a CoreTile Express A15x2. See
153 ARM DUI 0604E for details.
156 class Osc(RealViewOsc
):
157 site
, position
, dcc
= (1, 0, 0)
159 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
160 osc_cpu
= Osc(device
=0, freq
="60MHz")
161 osc_hsbm
= Osc(device
=4, freq
="40MHz")
162 osc_pxl
= Osc(device
=5, freq
="23.75MHz")
163 osc_smb
= Osc(device
=6, freq
="50MHz")
164 osc_sys
= Osc(device
=7, freq
="60MHz")
165 osc_ddr
= Osc(device
=8, freq
="40MHz")
167 class VGic(PioDevice
):
169 cxx_header
= "dev/arm/vgic.hh"
170 gic
= Param
.BaseGic(Parent
.any
, "Gic to use for interrupting")
171 platform
= Param
.Platform(Parent
.any
, "Platform this device is part of.")
172 vcpu_addr
= Param
.Addr(0, "Address for vcpu interfaces")
173 hv_addr
= Param
.Addr(0, "Address for hv control")
174 pio_delay
= Param
.Latency('10ns', "Delay for PIO r/w")
175 # The number of list registers is not currently configurable at runtime.
176 ppint
= Param
.UInt32("HV maintenance interrupt number")
178 class AmbaFake(AmbaPioDevice
):
180 cxx_header
= "dev/arm/amba_fake.hh"
181 ignore_access
= Param
.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
186 cxx_header
= "dev/arm/pl011.hh"
187 gic
= Param
.BaseGic(Parent
.any
, "Gic to use for interrupting")
188 int_num
= Param
.UInt32("Interrupt number that connects to GIC")
189 end_on_eot
= Param
.Bool(False, "End the simulation when a EOT is received on the UART")
190 int_delay
= Param
.Latency("100ns", "Time between action and interrupt generation by UART")
192 class Sp804(AmbaPioDevice
):
194 cxx_header
= "dev/arm/timer_sp804.hh"
195 gic
= Param
.BaseGic(Parent
.any
, "Gic to use for interrupting")
196 int_num0
= Param
.UInt32("Interrupt number that connects to GIC")
197 clock0
= Param
.Clock('1MHz', "Clock speed of the input")
198 int_num1
= Param
.UInt32("Interrupt number that connects to GIC")
199 clock1
= Param
.Clock('1MHz', "Clock speed of the input")
202 class CpuLocalTimer(BasicPioDevice
):
203 type = 'CpuLocalTimer'
204 cxx_header
= "dev/arm/timer_cpulocal.hh"
205 gic
= Param
.BaseGic(Parent
.any
, "Gic to use for interrupting")
206 int_num_timer
= Param
.UInt32("Interrrupt number used per-cpu to GIC")
207 int_num_watchdog
= Param
.UInt32("Interrupt number for per-cpu watchdog to GIC")
209 class GenericTimer(SimObject
):
210 type = 'GenericTimer'
211 cxx_header
= "dev/arm/generic_timer.hh"
212 system
= Param
.System(Parent
.any
, "system")
213 gic
= Param
.BaseGic(Parent
.any
, "GIC to use for interrupting")
214 # @todo: for now only two timers per CPU is supported, which is the
215 # normal behaviour when security extensions are disabled.
216 int_phys
= Param
.UInt32("Physical timer interrupt number")
217 int_virt
= Param
.UInt32("Virtual timer interrupt number")
219 class GenericTimerMem(PioDevice
):
220 type = 'GenericTimerMem'
221 cxx_header
= "dev/arm/generic_timer.hh"
222 gic
= Param
.BaseGic(Parent
.any
, "GIC to use for interrupting")
224 base
= Param
.Addr(0, "Base address")
226 int_phys
= Param
.UInt32("Interrupt number")
227 int_virt
= Param
.UInt32("Interrupt number")
229 class PL031(AmbaIntDevice
):
231 cxx_header
= "dev/arm/rtc_pl031.hh"
232 time
= Param
.Time('01/01/2009', "System time to use ('Now' for actual time)")
235 class Pl050(AmbaIntDevice
):
237 cxx_header
= "dev/arm/kmi.hh"
238 vnc
= Param
.VncInput(Parent
.any
, "Vnc server for remote frame buffer display")
239 is_mouse
= Param
.Bool(False, "Is this interface a mouse, if not a keyboard")
243 class Pl111(AmbaDmaDevice
):
245 cxx_header
= "dev/arm/pl111.hh"
246 pixel_clock
= Param
.Clock('24MHz', "Pixel clock")
247 vnc
= Param
.VncInput(Parent
.any
, "Vnc server for remote frame buffer display")
249 enable_capture
= Param
.Bool(True, "capture frame to system.framebuffer.bmp")
251 class HDLcd(AmbaDmaDevice
):
253 cxx_header
= "dev/arm/hdlcd.hh"
254 vnc
= Param
.VncInput(Parent
.any
, "Vnc server for remote frame buffer "
257 workaround_swap_rb
= Param
.Bool(False, "Workaround incorrect color "
258 "selector order in some kernels")
259 workaround_dma_line_count
= Param
.Bool(True, "Workaround incorrect "
260 "DMA line count (off by 1)")
261 enable_capture
= Param
.Bool(True, "capture frame to system.framebuffer.bmp")
263 pixel_buffer_size
= Param
.MemorySize32("2kB", "Size of address range")
265 pxl_clk
= Param
.ClockDomain("Pixel clock source")
266 pixel_chunk
= Param
.Unsigned(32, "Number of pixels to handle in one batch")
268 class RealView(Platform
):
270 cxx_header
= "dev/arm/realview.hh"
271 system
= Param
.System(Parent
.any
, "system")
272 _mem_regions
= [(Addr(0), Addr('256MB'))]
274 def attachPciDevices(self
):
277 def enableMSIX(self
):
280 def onChipIOClkDomain(self
, clkdomain
):
283 def offChipIOClkDomain(self
, clkdomain
):
286 def setupBootLoader(self
, mem_bus
, cur_sys
, loc
):
287 self
.nvmem
= SimpleMemory(range = AddrRange('2GB', size
= '64MB'),
288 conf_table_reported
= False)
289 self
.nvmem
.port
= mem_bus
.master
290 cur_sys
.boot_loader
= loc('boot.arm')
291 cur_sys
.atags_addr
= 0x100
292 cur_sys
.load_addr_mask
= 0xfffffff
293 cur_sys
.load_offset
= 0
296 # Reference for memory map and interrupt number
297 # RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
298 # Chapter 4: Programmer's Reference
299 class RealViewPBX(RealView
):
300 uart
= Pl011(pio_addr
=0x10009000, int_num
=44)
301 realview_io
= RealViewCtrl(pio_addr
=0x10000000)
303 dcc
= CoreTile2A15DCC()
305 pci_host
= GenericPciHost(
306 conf_base
=0x30000000, conf_size
='256MB', conf_device_bits
=16,
308 timer0
= Sp804(int_num0
=36, int_num1
=36, pio_addr
=0x10011000)
309 timer1
= Sp804(int_num0
=37, int_num1
=37, pio_addr
=0x10012000)
310 local_cpu_timer
= CpuLocalTimer(int_num_timer
=29, int_num_watchdog
=30, pio_addr
=0x1f000600)
311 clcd
= Pl111(pio_addr
=0x10020000, int_num
=55)
312 kmi0
= Pl050(pio_addr
=0x10006000, int_num
=52)
313 kmi1
= Pl050(pio_addr
=0x10007000, int_num
=53, is_mouse
=True)
314 a9scu
= A9SCU(pio_addr
=0x1f000000)
315 cf_ctrl
= IdeController(disks
=[], pci_func
=0, pci_dev
=7, pci_bus
=2,
316 io_shift
= 1, ctrl_offset
= 2, Command
= 0x1,
317 BAR0
= 0x18000000, BAR0Size
= '16B',
318 BAR1
= 0x18000100, BAR1Size
= '1B',
319 BAR0LegacyIO
= True, BAR1LegacyIO
= True)
322 l2x0_fake
= IsaFake(pio_addr
=0x1f002000, pio_size
=0xfff)
323 flash_fake
= IsaFake(pio_addr
=0x40000000, pio_size
=0x20000000,
325 dmac_fake
= AmbaFake(pio_addr
=0x10030000)
326 uart1_fake
= AmbaFake(pio_addr
=0x1000a000)
327 uart2_fake
= AmbaFake(pio_addr
=0x1000b000)
328 uart3_fake
= AmbaFake(pio_addr
=0x1000c000)
329 smc_fake
= AmbaFake(pio_addr
=0x100e1000)
330 sp810_fake
= AmbaFake(pio_addr
=0x10001000, ignore_access
=True)
331 watchdog_fake
= AmbaFake(pio_addr
=0x10010000)
332 gpio0_fake
= AmbaFake(pio_addr
=0x10013000)
333 gpio1_fake
= AmbaFake(pio_addr
=0x10014000)
334 gpio2_fake
= AmbaFake(pio_addr
=0x10015000)
335 ssp_fake
= AmbaFake(pio_addr
=0x1000d000)
336 sci_fake
= AmbaFake(pio_addr
=0x1000e000)
337 aaci_fake
= AmbaFake(pio_addr
=0x10004000)
338 mmc_fake
= AmbaFake(pio_addr
=0x10005000)
339 rtc
= PL031(pio_addr
=0x10017000, int_num
=42)
340 energy_ctrl
= EnergyCtrl(pio_addr
=0x1000f000)
343 # Attach I/O devices that are on chip and also set the appropriate
344 # ranges for the bridge
345 def attachOnChipIO(self
, bus
, bridge
):
346 self
.gic
.pio
= bus
.master
347 self
.l2x0_fake
.pio
= bus
.master
348 self
.a9scu
.pio
= bus
.master
349 self
.local_cpu_timer
.pio
= bus
.master
350 # Bridge ranges based on excluding what is part of on-chip I/O
351 # (gic, l2x0, a9scu, local_cpu_timer)
352 bridge
.ranges
= [AddrRange(self
.realview_io
.pio_addr
,
353 self
.a9scu
.pio_addr
- 1),
354 AddrRange(self
.flash_fake
.pio_addr
,
355 self
.flash_fake
.pio_addr
+ \
356 self
.flash_fake
.pio_size
- 1)]
358 # Set the clock domain for IO objects that are considered
359 # to be "close" to the cores.
360 def onChipIOClkDomain(self
, clkdomain
):
361 self
.gic
.clk_domain
= clkdomain
362 self
.l2x0_fake
.clk_domain
= clkdomain
363 self
.a9scu
.clkdomain
= clkdomain
364 self
.local_cpu_timer
.clk_domain
= clkdomain
366 # Attach I/O devices to specified bus object. Can't do this
367 # earlier, since the bus object itself is typically defined at the
369 def attachIO(self
, bus
):
370 self
.uart
.pio
= bus
.master
371 self
.realview_io
.pio
= bus
.master
372 self
.pci_host
.pio
= bus
.master
373 self
.timer0
.pio
= bus
.master
374 self
.timer1
.pio
= bus
.master
375 self
.clcd
.pio
= bus
.master
376 self
.clcd
.dma
= bus
.slave
377 self
.kmi0
.pio
= bus
.master
378 self
.kmi1
.pio
= bus
.master
379 self
.cf_ctrl
.pio
= bus
.master
380 self
.cf_ctrl
.dma
= bus
.slave
381 self
.dmac_fake
.pio
= bus
.master
382 self
.uart1_fake
.pio
= bus
.master
383 self
.uart2_fake
.pio
= bus
.master
384 self
.uart3_fake
.pio
= bus
.master
385 self
.smc_fake
.pio
= bus
.master
386 self
.sp810_fake
.pio
= bus
.master
387 self
.watchdog_fake
.pio
= bus
.master
388 self
.gpio0_fake
.pio
= bus
.master
389 self
.gpio1_fake
.pio
= bus
.master
390 self
.gpio2_fake
.pio
= bus
.master
391 self
.ssp_fake
.pio
= bus
.master
392 self
.sci_fake
.pio
= bus
.master
393 self
.aaci_fake
.pio
= bus
.master
394 self
.mmc_fake
.pio
= bus
.master
395 self
.rtc
.pio
= bus
.master
396 self
.flash_fake
.pio
= bus
.master
397 self
.energy_ctrl
.pio
= bus
.master
399 # Set the clock domain for IO objects that are considered
400 # to be "far" away from the cores.
401 def offChipIOClkDomain(self
, clkdomain
):
402 self
.uart
.clk_domain
= clkdomain
403 self
.realview_io
.clk_domain
= clkdomain
404 self
.timer0
.clk_domain
= clkdomain
405 self
.timer1
.clk_domain
= clkdomain
406 self
.clcd
.clk_domain
= clkdomain
407 self
.kmi0
.clk_domain
= clkdomain
408 self
.kmi1
.clk_domain
= clkdomain
409 self
.cf_ctrl
.clk_domain
= clkdomain
410 self
.dmac_fake
.clk_domain
= clkdomain
411 self
.uart1_fake
.clk_domain
= clkdomain
412 self
.uart2_fake
.clk_domain
= clkdomain
413 self
.uart3_fake
.clk_domain
= clkdomain
414 self
.smc_fake
.clk_domain
= clkdomain
415 self
.sp810_fake
.clk_domain
= clkdomain
416 self
.watchdog_fake
.clk_domain
= clkdomain
417 self
.gpio0_fake
.clk_domain
= clkdomain
418 self
.gpio1_fake
.clk_domain
= clkdomain
419 self
.gpio2_fake
.clk_domain
= clkdomain
420 self
.ssp_fake
.clk_domain
= clkdomain
421 self
.sci_fake
.clk_domain
= clkdomain
422 self
.aaci_fake
.clk_domain
= clkdomain
423 self
.mmc_fake
.clk_domain
= clkdomain
424 self
.rtc
.clk_domain
= clkdomain
425 self
.flash_fake
.clk_domain
= clkdomain
426 self
.energy_ctrl
.clk_domain
= clkdomain
428 # Reference for memory map and interrupt number
429 # RealView Emulation Baseboard User Guide (ARM DUI 0143B)
430 # Chapter 4: Programmer's Reference
431 class RealViewEB(RealView
):
432 uart
= Pl011(pio_addr
=0x10009000, int_num
=44)
433 realview_io
= RealViewCtrl(pio_addr
=0x10000000, idreg
=0x01400500)
435 dcc
= CoreTile2A15DCC()
436 gic
= Pl390(dist_addr
=0x10041000, cpu_addr
=0x10040000)
437 timer0
= Sp804(int_num0
=36, int_num1
=36, pio_addr
=0x10011000)
438 timer1
= Sp804(int_num0
=37, int_num1
=37, pio_addr
=0x10012000)
439 clcd
= Pl111(pio_addr
=0x10020000, int_num
=23)
440 kmi0
= Pl050(pio_addr
=0x10006000, int_num
=20)
441 kmi1
= Pl050(pio_addr
=0x10007000, int_num
=21, is_mouse
=True)
443 l2x0_fake
= IsaFake(pio_addr
=0x1f002000, pio_size
=0xfff, warn_access
="1")
444 flash_fake
= IsaFake(pio_addr
=0x40000000, pio_size
=0x20000000-1,
446 dmac_fake
= AmbaFake(pio_addr
=0x10030000)
447 uart1_fake
= AmbaFake(pio_addr
=0x1000a000)
448 uart2_fake
= AmbaFake(pio_addr
=0x1000b000)
449 uart3_fake
= AmbaFake(pio_addr
=0x1000c000)
450 smcreg_fake
= IsaFake(pio_addr
=0x10080000, pio_size
=0x10000-1)
451 smc_fake
= AmbaFake(pio_addr
=0x100e1000)
452 sp810_fake
= AmbaFake(pio_addr
=0x10001000, ignore_access
=True)
453 watchdog_fake
= AmbaFake(pio_addr
=0x10010000)
454 gpio0_fake
= AmbaFake(pio_addr
=0x10013000)
455 gpio1_fake
= AmbaFake(pio_addr
=0x10014000)
456 gpio2_fake
= AmbaFake(pio_addr
=0x10015000)
457 ssp_fake
= AmbaFake(pio_addr
=0x1000d000)
458 sci_fake
= AmbaFake(pio_addr
=0x1000e000)
459 aaci_fake
= AmbaFake(pio_addr
=0x10004000)
460 mmc_fake
= AmbaFake(pio_addr
=0x10005000)
461 rtc_fake
= AmbaFake(pio_addr
=0x10017000, amba_id
=0x41031)
462 energy_ctrl
= EnergyCtrl(pio_addr
=0x1000f000)
464 # Attach I/O devices that are on chip and also set the appropriate
465 # ranges for the bridge
466 def attachOnChipIO(self
, bus
, bridge
):
467 self
.gic
.pio
= bus
.master
468 self
.l2x0_fake
.pio
= bus
.master
469 # Bridge ranges based on excluding what is part of on-chip I/O
471 bridge
.ranges
= [AddrRange(self
.realview_io
.pio_addr
,
472 self
.gic
.cpu_addr
- 1),
473 AddrRange(self
.flash_fake
.pio_addr
, Addr
.max)]
475 # Set the clock domain for IO objects that are considered
476 # to be "close" to the cores.
477 def onChipIOClkDomain(self
, clkdomain
):
478 self
.gic
.clk_domain
= clkdomain
479 self
.l2x0_fake
.clk_domain
= clkdomain
481 # Attach I/O devices to specified bus object. Can't do this
482 # earlier, since the bus object itself is typically defined at the
484 def attachIO(self
, bus
):
485 self
.uart
.pio
= bus
.master
486 self
.realview_io
.pio
= bus
.master
487 self
.pci_host
.pio
= bus
.master
488 self
.timer0
.pio
= bus
.master
489 self
.timer1
.pio
= bus
.master
490 self
.clcd
.pio
= bus
.master
491 self
.clcd
.dma
= bus
.slave
492 self
.kmi0
.pio
= bus
.master
493 self
.kmi1
.pio
= bus
.master
494 self
.dmac_fake
.pio
= bus
.master
495 self
.uart1_fake
.pio
= bus
.master
496 self
.uart2_fake
.pio
= bus
.master
497 self
.uart3_fake
.pio
= bus
.master
498 self
.smc_fake
.pio
= bus
.master
499 self
.sp810_fake
.pio
= bus
.master
500 self
.watchdog_fake
.pio
= bus
.master
501 self
.gpio0_fake
.pio
= bus
.master
502 self
.gpio1_fake
.pio
= bus
.master
503 self
.gpio2_fake
.pio
= bus
.master
504 self
.ssp_fake
.pio
= bus
.master
505 self
.sci_fake
.pio
= bus
.master
506 self
.aaci_fake
.pio
= bus
.master
507 self
.mmc_fake
.pio
= bus
.master
508 self
.rtc_fake
.pio
= bus
.master
509 self
.flash_fake
.pio
= bus
.master
510 self
.smcreg_fake
.pio
= bus
.master
511 self
.energy_ctrl
.pio
= bus
.master
513 # Set the clock domain for IO objects that are considered
514 # to be "far" away from the cores.
515 def offChipIOClkDomain(self
, clkdomain
):
516 self
.uart
.clk_domain
= clkdomain
517 self
.realview_io
.clk_domain
= clkdomain
518 self
.timer0
.clk_domain
= clkdomain
519 self
.timer1
.clk_domain
= clkdomain
520 self
.clcd
.clk_domain
= clkdomain
521 self
.kmi0
.clk_domain
= clkdomain
522 self
.kmi1
.clk_domain
= clkdomain
523 self
.dmac_fake
.clk_domain
= clkdomain
524 self
.uart1_fake
.clk_domain
= clkdomain
525 self
.uart2_fake
.clk_domain
= clkdomain
526 self
.uart3_fake
.clk_domain
= clkdomain
527 self
.smc_fake
.clk_domain
= clkdomain
528 self
.sp810_fake
.clk_domain
= clkdomain
529 self
.watchdog_fake
.clk_domain
= clkdomain
530 self
.gpio0_fake
.clk_domain
= clkdomain
531 self
.gpio1_fake
.clk_domain
= clkdomain
532 self
.gpio2_fake
.clk_domain
= clkdomain
533 self
.ssp_fake
.clk_domain
= clkdomain
534 self
.sci_fake
.clk_domain
= clkdomain
535 self
.aaci_fake
.clk_domain
= clkdomain
536 self
.mmc_fake
.clk_domain
= clkdomain
537 self
.rtc
.clk_domain
= clkdomain
538 self
.flash_fake
.clk_domain
= clkdomain
539 self
.smcreg_fake
.clk_domain
= clkdomain
540 self
.energy_ctrl
.clk_domain
= clkdomain
542 class VExpress_EMM(RealView
):
543 _mem_regions
= [(Addr('2GB'), Addr('2GB'))]
544 uart
= Pl011(pio_addr
=0x1c090000, int_num
=37)
545 realview_io
= RealViewCtrl(
546 proc_id0
=0x14000000, proc_id1
=0x14000000,
547 idreg
=0x02250000, pio_addr
=0x1C010000)
549 dcc
= CoreTile2A15DCC()
550 gic
= Pl390(dist_addr
=0x2C001000, cpu_addr
=0x2C002000)
551 pci_host
= GenericPciHost(
552 conf_base
=0x30000000, conf_size
='256MB', conf_device_bits
=16,
554 local_cpu_timer
= CpuLocalTimer(int_num_timer
=29, int_num_watchdog
=30, pio_addr
=0x2C080000)
555 generic_timer
= GenericTimer(int_phys
=29, int_virt
=27)
556 timer0
= Sp804(int_num0
=34, int_num1
=34, pio_addr
=0x1C110000, clock0
='1MHz', clock1
='1MHz')
557 timer1
= Sp804(int_num0
=35, int_num1
=35, pio_addr
=0x1C120000, clock0
='1MHz', clock1
='1MHz')
558 clcd
= Pl111(pio_addr
=0x1c1f0000, int_num
=46)
559 hdlcd
= HDLcd(pxl_clk
=dcc
.osc_pxl
,
560 pio_addr
=0x2b000000, int_num
=117,
561 workaround_swap_rb
=True)
562 kmi0
= Pl050(pio_addr
=0x1c060000, int_num
=44)
563 kmi1
= Pl050(pio_addr
=0x1c070000, int_num
=45, is_mouse
=True)
564 vgic
= VGic(vcpu_addr
=0x2c006000, hv_addr
=0x2c004000, ppint
=25)
565 cf_ctrl
= IdeController(disks
=[], pci_func
=0, pci_dev
=0, pci_bus
=2,
566 io_shift
= 2, ctrl_offset
= 2, Command
= 0x1,
567 BAR0
= 0x1C1A0000, BAR0Size
= '256B',
568 BAR1
= 0x1C1A0100, BAR1Size
= '4096B',
569 BAR0LegacyIO
= True, BAR1LegacyIO
= True)
571 vram
= SimpleMemory(range = AddrRange(0x18000000, size
='32MB'),
572 conf_table_reported
= False)
573 rtc
= PL031(pio_addr
=0x1C170000, int_num
=36)
575 l2x0_fake
= IsaFake(pio_addr
=0x2C100000, pio_size
=0xfff)
576 uart1_fake
= AmbaFake(pio_addr
=0x1C0A0000)
577 uart2_fake
= AmbaFake(pio_addr
=0x1C0B0000)
578 uart3_fake
= AmbaFake(pio_addr
=0x1C0C0000)
579 sp810_fake
= AmbaFake(pio_addr
=0x1C020000, ignore_access
=True)
580 watchdog_fake
= AmbaFake(pio_addr
=0x1C0F0000)
581 aaci_fake
= AmbaFake(pio_addr
=0x1C040000)
582 lan_fake
= IsaFake(pio_addr
=0x1A000000, pio_size
=0xffff)
583 usb_fake
= IsaFake(pio_addr
=0x1B000000, pio_size
=0x1ffff)
584 mmc_fake
= AmbaFake(pio_addr
=0x1c050000)
585 energy_ctrl
= EnergyCtrl(pio_addr
=0x1c080000)
587 # Attach any PCI devices that are supported
588 def attachPciDevices(self
):
589 self
.ethernet
= IGbE_e1000(pci_bus
=0, pci_dev
=0, pci_func
=0,
590 InterruptLine
=1, InterruptPin
=1)
591 self
.ide
= IdeController(disks
= [], pci_bus
=0, pci_dev
=1, pci_func
=0,
592 InterruptLine
=2, InterruptPin
=2)
594 def enableMSIX(self
):
595 self
.gic
= Pl390(dist_addr
=0x2C001000, cpu_addr
=0x2C002000, it_lines
=512)
596 self
.gicv2m
= Gicv2m()
597 self
.gicv2m
.frames
= [Gicv2mFrame(spi_base
=256, spi_len
=64, addr
=0x2C1C0000)]
599 def setupBootLoader(self
, mem_bus
, cur_sys
, loc
):
600 self
.nvmem
= SimpleMemory(range = AddrRange('64MB'),
601 conf_table_reported
= False)
602 self
.nvmem
.port
= mem_bus
.master
603 cur_sys
.boot_loader
= loc('boot_emm.arm')
604 cur_sys
.atags_addr
= 0x8000000
605 cur_sys
.load_addr_mask
= 0xfffffff
606 cur_sys
.load_offset
= 0x80000000
608 # Attach I/O devices that are on chip and also set the appropriate
609 # ranges for the bridge
610 def attachOnChipIO(self
, bus
, bridge
=None):
611 self
.gic
.pio
= bus
.master
612 self
.vgic
.pio
= bus
.master
613 self
.local_cpu_timer
.pio
= bus
.master
614 if hasattr(self
, "gicv2m"):
615 self
.gicv2m
.pio
= bus
.master
616 self
.hdlcd
.dma
= bus
.slave
618 # Bridge ranges based on excluding what is part of on-chip I/O
620 bridge
.ranges
= [AddrRange(0x2F000000, size
='16MB'),
621 AddrRange(0x2B000000, size
='4MB'),
622 AddrRange(0x30000000, size
='256MB'),
623 AddrRange(0x40000000, size
='512MB'),
624 AddrRange(0x18000000, size
='64MB'),
625 AddrRange(0x1C000000, size
='64MB')]
628 # Set the clock domain for IO objects that are considered
629 # to be "close" to the cores.
630 def onChipIOClkDomain(self
, clkdomain
):
631 self
.gic
.clk_domain
= clkdomain
632 if hasattr(self
, "gicv2m"):
633 self
.gicv2m
.clk_domain
= clkdomain
634 self
.hdlcd
.clk_domain
= clkdomain
635 self
.vgic
.clk_domain
= clkdomain
637 # Attach I/O devices to specified bus object. Done here
638 # as the specified bus to connect to may not always be fixed.
639 def attachIO(self
, bus
):
640 self
.uart
.pio
= bus
.master
641 self
.realview_io
.pio
= bus
.master
642 self
.pci_host
.pio
= bus
.master
643 self
.timer0
.pio
= bus
.master
644 self
.timer1
.pio
= bus
.master
645 self
.clcd
.pio
= bus
.master
646 self
.clcd
.dma
= bus
.slave
647 self
.hdlcd
.pio
= bus
.master
648 self
.kmi0
.pio
= bus
.master
649 self
.kmi1
.pio
= bus
.master
650 self
.cf_ctrl
.pio
= bus
.master
651 self
.cf_ctrl
.dma
= bus
.slave
652 self
.rtc
.pio
= bus
.master
653 self
.vram
.port
= bus
.master
655 self
.l2x0_fake
.pio
= bus
.master
656 self
.uart1_fake
.pio
= bus
.master
657 self
.uart2_fake
.pio
= bus
.master
658 self
.uart3_fake
.pio
= bus
.master
659 self
.sp810_fake
.pio
= bus
.master
660 self
.watchdog_fake
.pio
= bus
.master
661 self
.aaci_fake
.pio
= bus
.master
662 self
.lan_fake
.pio
= bus
.master
663 self
.usb_fake
.pio
= bus
.master
664 self
.mmc_fake
.pio
= bus
.master
665 self
.energy_ctrl
.pio
= bus
.master
667 # Try to attach the I/O if it exists
669 self
.ide
.pio
= bus
.master
670 self
.ide
.dma
= bus
.slave
671 self
.ethernet
.pio
= bus
.master
672 self
.ethernet
.dma
= bus
.slave
676 # Set the clock domain for IO objects that are considered
677 # to be "far" away from the cores.
678 def offChipIOClkDomain(self
, clkdomain
):
679 self
.uart
.clk_domain
= clkdomain
680 self
.realview_io
.clk_domain
= clkdomain
681 self
.timer0
.clk_domain
= clkdomain
682 self
.timer1
.clk_domain
= clkdomain
683 self
.clcd
.clk_domain
= clkdomain
684 self
.kmi0
.clk_domain
= clkdomain
685 self
.kmi1
.clk_domain
= clkdomain
686 self
.cf_ctrl
.clk_domain
= clkdomain
687 self
.rtc
.clk_domain
= clkdomain
688 self
.vram
.clk_domain
= clkdomain
690 self
.l2x0_fake
.clk_domain
= clkdomain
691 self
.uart1_fake
.clk_domain
= clkdomain
692 self
.uart2_fake
.clk_domain
= clkdomain
693 self
.uart3_fake
.clk_domain
= clkdomain
694 self
.sp810_fake
.clk_domain
= clkdomain
695 self
.watchdog_fake
.clk_domain
= clkdomain
696 self
.aaci_fake
.clk_domain
= clkdomain
697 self
.lan_fake
.clk_domain
= clkdomain
698 self
.usb_fake
.clk_domain
= clkdomain
699 self
.mmc_fake
.clk_domain
= clkdomain
700 self
.energy_ctrl
.clk_domain
= clkdomain
702 class VExpress_EMM64(VExpress_EMM
):
703 # Three memory regions are specified totalling 512GB
704 _mem_regions
= [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
705 (Addr('512GB'), Addr('480GB'))]
706 pci_host
= GenericPciHost(
707 conf_base
=0x30000000, conf_size
='256MB', conf_device_bits
=12,
708 pci_pio_base
=0x2f000000)
710 def setupBootLoader(self
, mem_bus
, cur_sys
, loc
):
711 self
.nvmem
= SimpleMemory(range = AddrRange(0, size
= '64MB'))
712 self
.nvmem
.port
= mem_bus
.master
713 cur_sys
.boot_loader
= loc('boot_emm.arm64')
714 cur_sys
.atags_addr
= 0x8000000
715 cur_sys
.load_addr_mask
= 0xfffffff
716 cur_sys
.load_offset
= 0x80000000