src/dev/arm/RealView.py

   1 # Copyright (c) 2009-2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  14 # All rights reserved.
  15 #
  16 # Redistribution and use in source and binary forms, with or without
  17 # modification, are permitted provided that the following conditions are
  18 # met: redistributions of source code must retain the above copyright
  19 # notice, this list of conditions and the following disclaimer;
  20 # redistributions in binary form must reproduce the above copyright
  21 # notice, this list of conditions and the following disclaimer in the
  22 # documentation and/or other materials provided with the distribution;
  23 # neither the name of the copyright holders nor the names of its
  24 # contributors may be used to endorse or promote products derived from
  25 # this software without specific prior written permission.
  26 #
  27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Ali Saidi
  40 #          Gabe Black
  41 #          William Wang
  42 #          Glenn Bergmans
  43
  44 from m5.defines import buildEnv
  45 from m5.params import *
  46 from m5.proxy import *
  47 from m5.util.fdthelper import *
  48 from m5.objects.ClockDomain import ClockDomain
  49 from m5.objects.VoltageDomain import VoltageDomain
  50 from m5.objects.Device import \
  51     BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
  52 from m5.objects.PciHost import *
  53 from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000
  54 from m5.objects.Ide import *
  55 from m5.objects.Platform import Platform
  56 from m5.objects.Terminal import Terminal
  57 from m5.objects.Uart import Uart
  58 from m5.objects.SimpleMemory import SimpleMemory
  59 from m5.objects.Gic import *
  60 from m5.objects.EnergyCtrl import EnergyCtrl
  61 from m5.objects.ClockedObject import ClockedObject
  62 from m5.objects.ClockDomain import SrcClockDomain
  63 from m5.objects.SubSystem import SubSystem
  64 from m5.objects.Graphics import ImageFormat
  65 from m5.objects.ClockedObject import ClockedObject
  66 from m5.objects.PS2 import *
  67 from m5.objects.VirtIOMMIO import MmioVirtIO
  68 from m5.objects.Display import Display, Display1080p
  69
  70 # Platforms with KVM support should generally use in-kernel GIC
  71 # emulation. Use a GIC model that automatically switches between
  72 # gem5's GIC model and KVM's GIC model if KVM is available.
  73 try:
  74     from m5.objects.KvmGic import MuxingKvmGic
  75     kvm_gicv2_class = MuxingKvmGic
  76 except ImportError:
  77     # KVM support wasn't compiled into gem5. Fallback to a
  78     # software-only GIC.
  79     kvm_gicv2_class = Gic400
  80     pass
  81
  82 class AmbaPioDevice(BasicPioDevice):
  83     type = 'AmbaPioDevice'
  84     abstract = True
  85     cxx_header = "dev/arm/amba_device.hh"
  86     amba_id = Param.UInt32("ID of AMBA device for kernel detection")
  87
  88 class AmbaIntDevice(AmbaPioDevice):
  89     type = 'AmbaIntDevice'
  90     abstract = True
  91     cxx_header = "dev/arm/amba_device.hh"
  92     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
  93     int_num = Param.UInt32("Interrupt number that connects to GIC")
  94     int_delay = Param.Latency("100ns",
  95             "Time between action and interrupt generation by device")
  96
  97 class AmbaDmaDevice(DmaDevice):
  98     type = 'AmbaDmaDevice'
  99     abstract = True
 100     cxx_header = "dev/arm/amba_device.hh"
 101     pio_addr = Param.Addr("Address for AMBA slave interface")
 102     pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
 103     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
 104     int_num = Param.UInt32("Interrupt number that connects to GIC")
 105     amba_id = Param.UInt32("ID of AMBA device for kernel detection")
 106
 107 class A9SCU(BasicPioDevice):
 108     type = 'A9SCU'
 109     cxx_header = "dev/arm/a9scu.hh"
 110
 111 class ArmPciIntRouting(Enum): vals = [
 112     'ARM_PCI_INT_STATIC',
 113     'ARM_PCI_INT_DEV',
 114     'ARM_PCI_INT_PIN',
 115     ]
 116
 117 class GenericArmPciHost(GenericPciHost):
 118     type = 'GenericArmPciHost'
 119     cxx_header = "dev/arm/pci_host.hh"
 120
 121     int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
 122     int_base = Param.Unsigned("PCI interrupt base")
 123     int_count = Param.Unsigned("Maximum number of interrupts used by this host")
 124
 125     # This python parameter can be used in configuration scripts to turn
 126     # on/off the fdt dma-coherent flag when doing dtb autogeneration
 127     _dma_coherent = True
 128
 129     def generateDeviceTree(self, state):
 130         local_state = FdtState(
 131             addr_cells=3, size_cells=2,
 132             cpu_cells=1, interrupt_cells=1)
 133
 134         node = FdtNode("pci")
 135
 136         if int(self.conf_device_bits) == 8:
 137             node.appendCompatible("pci-host-cam-generic")
 138         elif int(self.conf_device_bits) == 12:
 139             node.appendCompatible("pci-host-ecam-generic")
 140         else:
 141             m5.fatal("No compatibility string for the set conf_device_width")
 142
 143         node.append(FdtPropertyStrings("device_type", ["pci"]))
 144
 145         # Cell sizes of child nodes/peripherals
 146         node.append(local_state.addrCellsProperty())
 147         node.append(local_state.sizeCellsProperty())
 148         node.append(local_state.interruptCellsProperty())
 149         # PCI address for CPU
 150         node.append(FdtPropertyWords("reg",
 151             state.addrCells(self.conf_base) +
 152             state.sizeCells(self.conf_size) ))
 153
 154         # Ranges mapping
 155         # For now some of this is hard coded, because the PCI module does not
 156         # have a proper full understanding of the memory map, but adapting the
 157         # PCI module is beyond the scope of what I'm trying to do here.
 158         # Values are taken from the VExpress_GEM5_V1 platform.
 159         ranges = []
 160         # Pio address range
 161         ranges += self.pciFdtAddr(space=1, addr=0)
 162         ranges += state.addrCells(self.pci_pio_base)
 163         ranges += local_state.sizeCells(0x10000)  # Fixed size
 164
 165         # AXI memory address range
 166         ranges += self.pciFdtAddr(space=2, addr=0)
 167         ranges += state.addrCells(0x40000000) # Fixed offset
 168         ranges += local_state.sizeCells(0x40000000) # Fixed size
 169         node.append(FdtPropertyWords("ranges", ranges))
 170
 171         if str(self.int_policy) == 'ARM_PCI_INT_DEV':
 172             gic = self._parent.unproxy(self).gic
 173             int_phandle = state.phandle(gic)
 174             # Interrupt mapping
 175             interrupts = []
 176
 177             # child interrupt specifier
 178             child_interrupt = local_state.interruptCells(0x0)
 179
 180             # parent unit address
 181             parent_addr = gic._state.addrCells(0x0)
 182
 183             for i in range(int(self.int_count)):
 184                 parent_interrupt = gic.interruptCells(0,
 185                     int(self.int_base) - 32 + i, 1)
 186
 187                 interrupts += self.pciFdtAddr(device=i, addr=0) + \
 188                     child_interrupt + [int_phandle] + parent_addr + \
 189                     parent_interrupt
 190
 191             node.append(FdtPropertyWords("interrupt-map", interrupts))
 192
 193             int_count = int(self.int_count)
 194             if int_count & (int_count - 1):
 195                 fatal("PCI interrupt count should be power of 2")
 196
 197             intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0]
 198             node.append(FdtPropertyWords("interrupt-map-mask", intmask))
 199         else:
 200             m5.fatal("Unsupported PCI interrupt policy " +
 201                      "for Device Tree generation")
 202
 203         if self._dma_coherent:
 204             node.append(FdtProperty("dma-coherent"))
 205
 206         yield node
 207
 208 class RealViewCtrl(BasicPioDevice):
 209     type = 'RealViewCtrl'
 210     cxx_header = "dev/arm/rv_ctrl.hh"
 211     proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
 212     proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
 213     idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
 214
 215     def generateDeviceTree(self, state):
 216         node = FdtNode("sysreg@%x" % long(self.pio_addr))
 217         node.appendCompatible("arm,vexpress-sysreg")
 218         node.append(FdtPropertyWords("reg",
 219             state.addrCells(self.pio_addr) +
 220             state.sizeCells(0x1000) ))
 221         node.append(FdtProperty("gpio-controller"))
 222         node.append(FdtPropertyWords("#gpio-cells", [2]))
 223         node.appendPhandle(self)
 224
 225         yield node
 226
 227 class RealViewOsc(ClockDomain):
 228     type = 'RealViewOsc'
 229     cxx_header = "dev/arm/rv_ctrl.hh"
 230
 231     parent = Param.RealViewCtrl(Parent.any, "RealView controller")
 232
 233     # TODO: We currently don't have the notion of a clock source,
 234     # which means we have to associate oscillators with a voltage
 235     # source.
 236     voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
 237                                          "Voltage domain")
 238
 239     # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
 240     # the individual core/logic tile reference manuals for details
 241     # about the site/position/dcc/device allocation.
 242     site = Param.UInt8("Board Site")
 243     position = Param.UInt8("Position in device stack")
 244     dcc = Param.UInt8("Daughterboard Configuration Controller")
 245     device = Param.UInt8("Device ID")
 246
 247     freq = Param.Clock("Default frequency")
 248
 249     def generateDeviceTree(self, state):
 250         phandle = state.phandle(self)
 251         node = FdtNode("osc@" + format(long(phandle), 'x'))
 252         node.appendCompatible("arm,vexpress-osc")
 253         node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
 254                                      [0x1, int(self.device)]))
 255         node.append(FdtPropertyWords("#clock-cells", [0]))
 256         freq = int(1.0/self.freq.value) # Values are stored as a clock period
 257         node.append(FdtPropertyWords("freq-range", [freq, freq]))
 258         node.append(FdtPropertyStrings("clock-output-names",
 259                                        ["oscclk" + str(phandle)]))
 260         node.appendPhandle(self)
 261         yield node
 262
 263 class RealViewTemperatureSensor(SimObject):
 264     type = 'RealViewTemperatureSensor'
 265     cxx_header = "dev/arm/rv_ctrl.hh"
 266
 267     parent = Param.RealViewCtrl(Parent.any, "RealView controller")
 268
 269     system = Param.System(Parent.any, "system")
 270
 271     # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
 272     # the individual core/logic tile reference manuals for details
 273     # about the site/position/dcc/device allocation.
 274     site = Param.UInt8("Board Site")
 275     position = Param.UInt8("Position in device stack")
 276     dcc = Param.UInt8("Daughterboard Configuration Controller")
 277     device = Param.UInt8("Device ID")
 278
 279 class VExpressMCC(SubSystem):
 280     """ARM V2M-P1 Motherboard Configuration Controller
 281
 282 This subsystem describes a subset of the devices that sit behind the
 283 motherboard configuration controller on the the ARM Motherboard
 284 Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
 285     """
 286
 287     class Osc(RealViewOsc):
 288         site, position, dcc = (0, 0, 0)
 289
 290     class Temperature(RealViewTemperatureSensor):
 291         site, position, dcc = (0, 0, 0)
 292
 293     osc_mcc = Osc(device=0, freq="50MHz")
 294     osc_clcd = Osc(device=1, freq="23.75MHz")
 295     osc_peripheral = Osc(device=2, freq="24MHz")
 296     osc_system_bus = Osc(device=4, freq="24MHz")
 297
 298     # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
 299     temp_crtl = Temperature(device=0)
 300
 301     def generateDeviceTree(self, state):
 302         node = FdtNode("mcc")
 303         node.appendCompatible("arm,vexpress,config-bus")
 304         node.append(FdtPropertyWords("arm,vexpress,site", [0]))
 305
 306         for obj in self._children.values():
 307             if issubclass(type(obj), SimObject):
 308                 node.append(obj.generateDeviceTree(state))
 309
 310         io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self))
 311         node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
 312
 313         yield node
 314
 315 class CoreTile2A15DCC(SubSystem):
 316     """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
 317
 318 This subsystem describes a subset of the devices that sit behind the
 319 daughterboard configuration controller on a CoreTile Express A15x2. See
 320 ARM DUI 0604E for details.
 321     """
 322
 323     class Osc(RealViewOsc):
 324         site, position, dcc = (1, 0, 0)
 325
 326     # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
 327     osc_cpu = Osc(device=0, freq="60MHz")
 328     osc_hsbm = Osc(device=4, freq="40MHz")
 329     osc_pxl = Osc(device=5, freq="23.75MHz")
 330     osc_smb = Osc(device=6, freq="50MHz")
 331     osc_sys = Osc(device=7, freq="60MHz")
 332     osc_ddr = Osc(device=8, freq="40MHz")
 333
 334     def generateDeviceTree(self, state):
 335         node = FdtNode("dcc")
 336         node.appendCompatible("arm,vexpress,config-bus")
 337
 338         for obj in self._children.values():
 339             if isinstance(obj, SimObject):
 340                 node.append(obj.generateDeviceTree(state))
 341
 342         io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self))
 343         node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle))
 344
 345         yield node
 346
 347 class AmbaFake(AmbaPioDevice):
 348     type = 'AmbaFake'
 349     cxx_header = "dev/arm/amba_fake.hh"
 350     ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
 351     amba_id = 0;
 352
 353 class Pl011(Uart):
 354     type = 'Pl011'
 355     cxx_header = "dev/arm/pl011.hh"
 356     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
 357     int_num = Param.UInt32("Interrupt number that connects to GIC")
 358     end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
 359     int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
 360
 361     def generateDeviceTree(self, state):
 362         node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr,
 363                                                0x1000, [int(self.int_num)])
 364         node.appendCompatible(["arm,pl011", "arm,primecell"])
 365
 366         # Hardcoded reference to the realview platform clocks, because the
 367         # clk_domain can only store one clock (i.e. it is not a VectorParam)
 368         realview = self._parent.unproxy(self)
 369         node.append(FdtPropertyWords("clocks",
 370             [state.phandle(realview.mcc.osc_peripheral),
 371             state.phandle(realview.dcc.osc_smb)]))
 372         node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"]))
 373         yield node
 374
 375 class Sp804(AmbaPioDevice):
 376     type = 'Sp804'
 377     cxx_header = "dev/arm/timer_sp804.hh"
 378     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
 379     int_num0 = Param.UInt32("Interrupt number that connects to GIC")
 380     clock0 = Param.Clock('1MHz', "Clock speed of the input")
 381     int_num1 = Param.UInt32("Interrupt number that connects to GIC")
 382     clock1 = Param.Clock('1MHz', "Clock speed of the input")
 383     amba_id = 0x00141804
 384
 385 class A9GlobalTimer(BasicPioDevice):
 386     type = 'A9GlobalTimer'
 387     cxx_header = "dev/arm/timer_a9global.hh"
 388     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
 389     int_num = Param.UInt32("Interrrupt number that connects to GIC")
 390
 391 class CpuLocalTimer(BasicPioDevice):
 392     type = 'CpuLocalTimer'
 393     cxx_header = "dev/arm/timer_cpulocal.hh"
 394     int_timer = Param.ArmPPI("Interrrupt used per-cpu to GIC")
 395     int_watchdog = Param.ArmPPI("Interrupt for per-cpu watchdog to GIC")
 396
 397 class GenericTimer(ClockedObject):
 398     type = 'GenericTimer'
 399     cxx_header = "dev/arm/generic_timer.hh"
 400     system = Param.ArmSystem(Parent.any, "system")
 401     int_phys_s = Param.ArmPPI("Physical (S) timer interrupt")
 402     int_phys_ns = Param.ArmPPI("Physical (NS) timer interrupt")
 403     int_virt = Param.ArmPPI("Virtual timer interrupt")
 404     int_hyp = Param.ArmPPI("Hypervisor timer interrupt")
 405
 406     def generateDeviceTree(self, state):
 407         node = FdtNode("timer")
 408
 409         node.appendCompatible(["arm,cortex-a15-timer",
 410                                "arm,armv7-timer",
 411                                "arm,armv8-timer"])
 412         node.append(FdtPropertyWords("interrupts", [
 413             1, int(self.int_phys_s.num) - 16, 0xf08,
 414             1, int(self.int_phys_ns.num) - 16, 0xf08,
 415             1, int(self.int_virt.num) - 16, 0xf08,
 416             1, int(self.int_hyp.num) - 16, 0xf08,
 417         ]))
 418         clock = state.phandle(self.clk_domain.unproxy(self))
 419         node.append(FdtPropertyWords("clocks", clock))
 420
 421         yield node
 422
 423 class GenericTimerMem(PioDevice):
 424     type = 'GenericTimerMem'
 425     cxx_header = "dev/arm/generic_timer.hh"
 426
 427     base = Param.Addr(0, "Base address")
 428
 429     int_phys = Param.ArmSPI("Physical Interrupt")
 430     int_virt = Param.ArmSPI("Virtual Interrupt")
 431
 432 class PL031(AmbaIntDevice):
 433     type = 'PL031'
 434     cxx_header = "dev/arm/rtc_pl031.hh"
 435     time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
 436     amba_id = 0x00341031
 437
 438     def generateDeviceTree(self, state):
 439         node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
 440                                                0x1000, [int(self.int_num)])
 441
 442         node.appendCompatible(["arm,pl031", "arm,primecell"])
 443         clock = state.phandle(self.clk_domain.unproxy(self))
 444         node.append(FdtPropertyWords("clocks", clock))
 445
 446         yield node
 447
 448 class Pl050(AmbaIntDevice):
 449     type = 'Pl050'
 450     cxx_header = "dev/arm/kmi.hh"
 451     amba_id = 0x00141050
 452
 453     ps2 = Param.PS2Device("PS/2 device")
 454
 455     def generateDeviceTree(self, state):
 456         node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
 457                                                0x1000, [int(self.int_num)])
 458
 459         node.appendCompatible(["arm,pl050", "arm,primecell"])
 460         clock = state.phandle(self.clk_domain.unproxy(self))
 461         node.append(FdtPropertyWords("clocks", clock))
 462
 463         yield node
 464
 465 class Pl111(AmbaDmaDevice):
 466     type = 'Pl111'
 467     cxx_header = "dev/arm/pl111.hh"
 468     pixel_clock = Param.Clock('24MHz', "Pixel clock")
 469     vnc   = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
 470     amba_id = 0x00141111
 471     enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
 472
 473 class HDLcd(AmbaDmaDevice):
 474     type = 'HDLcd'
 475     cxx_header = "dev/arm/hdlcd.hh"
 476     vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
 477                                      "display")
 478     amba_id = 0x00141000
 479     workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
 480                                     "selector order in some kernels")
 481     workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
 482                                            "DMA line count (off by 1)")
 483     enable_capture = Param.Bool(True, "capture frame to "
 484                                       "system.framebuffer.{extension}")
 485     frame_format = Param.ImageFormat("Auto",
 486                                      "image format of the captured frame")
 487
 488     pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
 489
 490     pxl_clk = Param.ClockDomain("Pixel clock source")
 491     pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
 492     virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
 493                                         "in KVM mode")
 494     _status = "disabled"
 495
 496     encoder = Param.Display(Display1080p(), "Display encoder")
 497
 498     def endpointPhandle(self):
 499         return "hdlcd_endpoint"
 500
 501     def generateDeviceTree(self, state):
 502         endpoint_node = FdtNode("endpoint")
 503         endpoint_node.appendPhandle(self.endpointPhandle())
 504
 505         for encoder_node in self.encoder.generateDeviceTree(state):
 506             encoder_endpoint = self.encoder.endpointNode()
 507
 508             # Endpoint subnode
 509             endpoint_node.append(FdtPropertyWords("remote-endpoint",
 510                 [ state.phandle(self.encoder.endpointPhandle()) ]))
 511             encoder_endpoint.append(FdtPropertyWords("remote-endpoint",
 512                 [ state.phandle(self.endpointPhandle()) ]))
 513
 514             yield encoder_node
 515
 516         port_node = FdtNode("port")
 517         port_node.append(endpoint_node)
 518
 519         # Interrupt number is hardcoded; it is not a property of this class
 520         node = self.generateBasicPioDeviceNode(state, 'hdlcd',
 521                                                self.pio_addr, 0x1000, [63])
 522
 523         node.appendCompatible(["arm,hdlcd"])
 524         node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk)))
 525         node.append(FdtPropertyStrings("clock-names", ["pxlclk"]))
 526
 527         # This driver is disabled by default since the required DT nodes
 528         # haven't been standardized yet. To use it,  override this status to
 529         # "ok" and add the display configuration nodes required by the driver.
 530         # See the driver for more information.
 531         node.append(FdtPropertyStrings("status", [ self._status ]))
 532
 533         self.addIommuProperty(state, node)
 534
 535         node.append(port_node)
 536
 537         yield node
 538
 539 class RealView(Platform):
 540     type = 'RealView'
 541     cxx_header = "dev/arm/realview.hh"
 542     system = Param.System(Parent.any, "system")
 543     _mem_regions = [ AddrRange(0, size='256MB') ]
 544
 545     def _on_chip_devices(self):
 546         return []
 547
 548     def _off_chip_devices(self):
 549         return []
 550
 551     _off_chip_ranges = []
 552
 553     def _attach_memory(self, mem, bus, mem_ports=None):
 554         if hasattr(mem, "port"):
 555             if mem_ports is None:
 556                 mem.port = bus.master
 557             else:
 558                 mem_ports.append(mem.port)
 559
 560     def _attach_device(self, device, bus, dma_ports=None):
 561         if hasattr(device, "pio"):
 562             device.pio = bus.master
 563         if hasattr(device, "dma"):
 564             if dma_ports is None:
 565                 device.dma = bus.slave
 566             else:
 567                 dma_ports.append(device.dma)
 568
 569     def _attach_io(self, devices, *args, **kwargs):
 570         for d in devices:
 571             self._attach_device(d, *args, **kwargs)
 572
 573     def _attach_mem(self, memories, *args, **kwargs):
 574         for mem in memories:
 575             self._attach_memory(mem, *args, **kwargs)
 576
 577     def _attach_clk(self, devices, clkdomain):
 578         for d in devices:
 579             if hasattr(d, "clk_domain"):
 580                 d.clk_domain = clkdomain
 581
 582     def attachPciDevices(self):
 583         pass
 584
 585     def enableMSIX(self):
 586         pass
 587
 588     def onChipIOClkDomain(self, clkdomain):
 589         self._attach_clk(self._on_chip_devices(), clkdomain)
 590
 591     def offChipIOClkDomain(self, clkdomain):
 592         self._attach_clk(self._off_chip_devices(), clkdomain)
 593
 594     def attachOnChipIO(self, bus, bridge=None, dma_ports=None, mem_ports=None):
 595         self._attach_mem(self._on_chip_memory(), bus, mem_ports)
 596         self._attach_io(self._on_chip_devices(), bus, dma_ports)
 597         if bridge:
 598             bridge.ranges = self._off_chip_ranges
 599
 600     def attachIO(self, *args, **kwargs):
 601         self._attach_io(self._off_chip_devices(), *args, **kwargs)
 602
 603     def setupBootLoader(self, cur_sys, loc):
 604         cur_sys.boot_loader = loc('boot.arm')
 605         cur_sys.atags_addr = 0x100
 606         cur_sys.load_offset = 0
 607
 608     def generateDeviceTree(self, state):
 609         node = FdtNode("/") # Things in this module need to end up in the root
 610         node.append(FdtPropertyWords("interrupt-parent",
 611                                      state.phandle(self.gic)))
 612
 613         for subnode in self.recurseDeviceTree(state):
 614             node.append(subnode)
 615
 616         yield node
 617
 618     def annotateCpuDeviceNode(self, cpu, state):
 619         cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
 620         cpu.append(FdtPropertyWords("cpu-release-addr", \
 621                                     state.addrCells(0x8000fff8)))
 622
 623 class VExpress_EMM(RealView):
 624     _mem_regions = [ AddrRange('2GB', size='2GB') ]
 625
 626     # Ranges based on excluding what is part of on-chip I/O (gic,
 627     # a9scu)
 628     _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
 629                         AddrRange(0x30000000, size='256MB'),
 630                         AddrRange(0x40000000, size='512MB'),
 631                         AddrRange(0x18000000, size='64MB'),
 632                         AddrRange(0x1C000000, size='64MB')]
 633
 634     # Platform control device (off-chip)
 635     realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
 636                                idreg=0x02250000, pio_addr=0x1C010000)
 637
 638     mcc = VExpressMCC()
 639     dcc = CoreTile2A15DCC()
 640
 641     ### On-chip devices ###
 642     gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000)
 643     vgic   = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, maint_int=25)
 644
 645     local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29),
 646                                     int_watchdog=ArmPPI(num=30),
 647                                     pio_addr=0x2C080000)
 648
 649     hdlcd  = HDLcd(pxl_clk=dcc.osc_pxl,
 650                    pio_addr=0x2b000000, int_num=117,
 651                    workaround_swap_rb=True)
 652
 653     def _on_chip_devices(self):
 654         devices = [
 655             self.gic, self.vgic,
 656             self.local_cpu_timer
 657         ]
 658         if hasattr(self, "gicv2m"):
 659             devices.append(self.gicv2m)
 660         devices.append(self.hdlcd)
 661         return devices
 662
 663     def _on_chip_memory(self):
 664         memories = [
 665             self.bootmem,
 666         ]
 667         return memories
 668
 669     ### Off-chip devices ###
 670     uart = Pl011(pio_addr=0x1c090000, int_num=37)
 671     pci_host = GenericPciHost(
 672         conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
 673         pci_pio_base=0)
 674
 675     generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29),
 676                                  int_phys_ns=ArmPPI(num=30),
 677                                  int_virt=ArmPPI(num=27),
 678                                  int_hyp=ArmPPI(num=26))
 679
 680     timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
 681     timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
 682     clcd   = Pl111(pio_addr=0x1c1f0000, int_num=46)
 683     kmi0   = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
 684     kmi1   = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
 685     cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
 686                             io_shift = 2, ctrl_offset = 2, Command = 0x1,
 687                             BAR0 = 0x1C1A0000, BAR0Size = '256B',
 688                             BAR1 = 0x1C1A0100, BAR1Size = '4096B',
 689                             BAR0LegacyIO = True, BAR1LegacyIO = True)
 690
 691     bootmem        = SimpleMemory(range = AddrRange('64MB'),
 692                                   conf_table_reported = False)
 693     vram           = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
 694                                   conf_table_reported = False)
 695     rtc            = PL031(pio_addr=0x1C170000, int_num=36)
 696
 697     l2x0_fake      = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
 698     uart1_fake     = AmbaFake(pio_addr=0x1C0A0000)
 699     uart2_fake     = AmbaFake(pio_addr=0x1C0B0000)
 700     uart3_fake     = AmbaFake(pio_addr=0x1C0C0000)
 701     sp810_fake     = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
 702     watchdog_fake  = AmbaFake(pio_addr=0x1C0F0000)
 703     aaci_fake      = AmbaFake(pio_addr=0x1C040000)
 704     lan_fake       = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
 705     usb_fake       = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
 706     mmc_fake       = AmbaFake(pio_addr=0x1c050000)
 707     energy_ctrl    = EnergyCtrl(pio_addr=0x1c080000)
 708
 709     def _off_chip_devices(self):
 710         devices = [
 711             self.uart,
 712             self.realview_io,
 713             self.pci_host,
 714             self.timer0,
 715             self.timer1,
 716             self.clcd,
 717             self.kmi0,
 718             self.kmi1,
 719             self.cf_ctrl,
 720             self.rtc,
 721             self.vram,
 722             self.l2x0_fake,
 723             self.uart1_fake,
 724             self.uart2_fake,
 725             self.uart3_fake,
 726             self.sp810_fake,
 727             self.watchdog_fake,
 728             self.aaci_fake,
 729             self.lan_fake,
 730             self.usb_fake,
 731             self.mmc_fake,
 732             self.energy_ctrl,
 733         ]
 734         # Try to attach the I/O if it exists
 735         if hasattr(self, "ide"):
 736             devices.append(self.ide)
 737         if hasattr(self, "ethernet"):
 738             devices.append(self.ethernet)
 739         return devices
 740
 741     # Attach any PCI devices that are supported
 742     def attachPciDevices(self):
 743         self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
 744                                    InterruptLine=1, InterruptPin=1)
 745         self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
 746                                  InterruptLine=2, InterruptPin=2)
 747
 748     def enableMSIX(self):
 749         self.gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000,
 750                           it_lines=512)
 751         self.gicv2m = Gicv2m()
 752         self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
 753
 754     def setupBootLoader(self, cur_sys, loc):
 755         if not cur_sys.boot_loader:
 756             cur_sys.boot_loader = loc('boot_emm.arm')
 757         cur_sys.atags_addr = 0x8000000
 758         cur_sys.load_offset = 0x80000000
 759
 760 class VExpress_EMM64(VExpress_EMM):
 761     # Three memory regions are specified totalling 512GB
 762     _mem_regions = [ AddrRange('2GB', size='2GB'),
 763                      AddrRange('34GB', size='30GB'),
 764                      AddrRange('512GB', size='480GB') ]
 765     pci_host = GenericPciHost(
 766         conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
 767         pci_pio_base=0x2f000000)
 768
 769     def setupBootLoader(self, cur_sys, loc):
 770         if not cur_sys.boot_loader:
 771             cur_sys.boot_loader = loc('boot_emm.arm64')
 772         cur_sys.atags_addr = 0x8000000
 773         cur_sys.load_offset = 0x80000000
 774
 775 class VExpress_GEM5_Base(RealView):
 776     """
 777 The VExpress gem5 memory map is loosely based on a modified
 778 Versatile Express RS1 memory map.
 779
 780 The gem5 platform has been designed to implement a subset of the
 781 original Versatile Express RS1 memory map. Off-chip peripherals should,
 782 when possible, adhere to the Versatile Express memory map. Non-PCI
 783 off-chip devices that are gem5-specific should live in the CS5 memory
 784 space to avoid conflicts with existing devices that we might want to
 785 model in the future. Such devices should normally have interrupts in
 786 the gem5-specific SPI range.
 787
 788 On-chip peripherals are loosely modeled after the ARM CoreTile Express
 789 A15x2 A7x3 memory and interrupt map. In particular, the GIC and
 790 Generic Timer have the same interrupt lines and base addresses. Other
 791 on-chip devices are gem5 specific.
 792
 793 Unlike the original Versatile Express RS2 extended platform, gem5 implements a
 794 large contigious DRAM space, without aliases or holes, starting at the
 795 2GiB boundary. This means that PCI memory is limited to 1GiB.
 796
 797 Memory map:
 798    0x00000000-0x03ffffff: Boot memory (CS0)
 799    0x04000000-0x07ffffff: Reserved
 800    0x08000000-0x0bffffff: Reserved (CS0 alias)
 801    0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
 802    0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
 803        0x10000000-0x1000ffff: gem5 energy controller
 804        0x10010000-0x1001ffff: gem5 pseudo-ops
 805
 806    0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
 807    0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
 808    0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
 809        0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
 810        0x1c060000-0x1c06ffff: KMI0 (keyboard)
 811        0x1c070000-0x1c07ffff: KMI1 (mouse)
 812        0x1c090000-0x1c09ffff: UART0
 813        0x1c0a0000-0x1c0affff: UART1 (reserved)
 814        0x1c0b0000-0x1c0bffff: UART2 (reserved)
 815        0x1c0c0000-0x1c0cffff: UART3 (reserved)
 816        0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
 817        0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
 818        0x1c170000-0x1c17ffff: RTC
 819
 820    0x20000000-0x3fffffff: On-chip peripherals:
 821        0x2b000000-0x2b00ffff: HDLCD
 822
 823        0x2c001000-0x2c001fff: GIC (distributor)
 824        0x2c002000-0x2c003fff: GIC (CPU interface)
 825        0x2c004000-0x2c005fff: vGIC (HV)
 826        0x2c006000-0x2c007fff: vGIC (VCPU)
 827        0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
 828
 829        0x2d000000-0x2d00ffff: GPU (reserved)
 830
 831        0x2f000000-0x2fffffff: PCI IO space
 832        0x30000000-0x3fffffff: PCI config space
 833
 834    0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
 835
 836    0x80000000-X: DRAM
 837
 838 Interrupts:
 839       0- 15: Software generated interrupts (SGIs)
 840      16- 31: On-chip private peripherals (PPIs)
 841         25   : vgic
 842         26   : generic_timer (hyp)
 843         27   : generic_timer (virt)
 844         28   : Reserved (Legacy FIQ)
 845         29   : generic_timer (phys, sec)
 846         30   : generic_timer (phys, non-sec)
 847         31   : Reserved (Legacy IRQ)
 848     32- 95: Mother board peripherals (SPIs)
 849         32   : Reserved (SP805)
 850         33   : Reserved (IOFPGA SW int)
 851         34-35: Reserved (SP804)
 852         36   : RTC
 853         37-40: uart0-uart3
 854         41-42: Reserved (PL180)
 855         43   : Reserved (AACI)
 856         44-45: kmi0-kmi1
 857         46   : Reserved (CLCD)
 858         47   : Reserved (Ethernet)
 859         48   : Reserved (USB)
 860     95-255: On-chip interrupt sources (we use these for
 861             gem5-specific devices, SPIs)
 862          74    : VirtIO (gem5/FM extension)
 863          75    : VirtIO (gem5/FM extension)
 864          95    : HDLCD
 865          96- 98: GPU (reserved)
 866         100-103: PCI
 867    256-319: MSI frame 0 (gem5-specific, SPIs)
 868    320-511: Unused
 869
 870     """
 871
 872     # Everything above 2GiB is memory
 873     _mem_regions = [ AddrRange('2GB', size='510GB') ]
 874
 875     _off_chip_ranges = [
 876         # CS1-CS5
 877         AddrRange(0x0c000000, 0x1fffffff),
 878         # External AXI interface (PCI)
 879         AddrRange(0x2f000000, 0x7fffffff),
 880     ]
 881
 882     bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
 883                            conf_table_reported=False)
 884
 885     # Platform control device (off-chip)
 886     realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
 887                                idreg=0x02250000, pio_addr=0x1c010000)
 888     mcc = VExpressMCC()
 889     dcc = CoreTile2A15DCC()
 890
 891     ### On-chip devices ###
 892     generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29),
 893                                  int_phys_ns=ArmPPI(num=30),
 894                                  int_virt=ArmPPI(num=27),
 895                                  int_hyp=ArmPPI(num=26))
 896
 897     def _on_chip_devices(self):
 898         return [
 899             self.generic_timer,
 900         ]
 901
 902     def _on_chip_memory(self):
 903         memories = [
 904             self.bootmem,
 905         ]
 906         return memories
 907
 908     ### Off-chip devices ###
 909     clock24MHz = SrcClockDomain(clock="24MHz",
 910         voltage_domain=VoltageDomain(voltage="3.3V"))
 911
 912     uart = [
 913         Pl011(pio_addr=0x1c090000, int_num=37),
 914     ]
 915
 916     kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
 917     kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
 918
 919     rtc = PL031(pio_addr=0x1c170000, int_num=36)
 920
 921     ### gem5-specific off-chip devices ###
 922     pci_host = GenericArmPciHost(
 923         conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
 924         pci_pio_base=0x2f000000,
 925         int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
 926
 927     energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
 928
 929     vio = [
 930         MmioVirtIO(pio_addr=0x1c130000, pio_size=0x1000,
 931                    interrupt=ArmSPI(num=74)),
 932         MmioVirtIO(pio_addr=0x1c140000, pio_size=0x1000,
 933                    interrupt=ArmSPI(num=75)),
 934     ]
 935
 936     def _off_chip_devices(self):
 937         return [
 938             self.realview_io,
 939             self.uart[0],
 940             self.kmi0,
 941             self.kmi1,
 942             self.rtc,
 943             self.pci_host,
 944             self.energy_ctrl,
 945             self.clock24MHz,
 946             self.vio[0],
 947             self.vio[1],
 948         ]
 949
 950     def attachPciDevice(self, device, *args, **kwargs):
 951         device.host = self.pci_host
 952         self._attach_device(device, *args, **kwargs)
 953
 954     def setupBootLoader(self, cur_sys, loc):
 955         if not cur_sys.boot_loader:
 956             cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
 957         cur_sys.atags_addr = 0x8000000
 958         cur_sys.load_offset = 0x80000000
 959
 960         #  Setup m5ops. It's technically not a part of the boot
 961         #  loader, but this is the only place we can configure the
 962         #  system.
 963         cur_sys.m5ops_base = 0x10010000
 964
 965     def generateDeviceTree(self, state):
 966         # Generate using standard RealView function
 967         dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state))
 968         if len(dt) > 1:
 969             raise Exception("System returned too many DT nodes")
 970         node = dt[0]
 971
 972         node.appendCompatible(["arm,vexpress"])
 973         node.append(FdtPropertyStrings("model", ["V2P-CA15"]))
 974         node.append(FdtPropertyWords("arm,hbi", [0x0]))
 975         node.append(FdtPropertyWords("arm,vexpress,site", [0xf]))
 976
 977         yield node
 978
 979 class VExpress_GEM5_V1_Base(VExpress_GEM5_Base):
 980     gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
 981                           it_lines=512)
 982     vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, maint_int=25)
 983     gicv2m = Gicv2m()
 984     gicv2m.frames = [
 985         Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
 986     ]
 987
 988     def _on_chip_devices(self):
 989         return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [
 990                 self.gic, self.vgic, self.gicv2m,
 991             ]
 992
 993 class VExpress_GEM5_V1(VExpress_GEM5_V1_Base):
 994     hdlcd  = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl,
 995                    pio_addr=0x2b000000, int_num=95)
 996
 997     def _on_chip_devices(self):
 998         return super(VExpress_GEM5_V1,self)._on_chip_devices() + [
 999                 self.hdlcd,
1000             ]
1001
1002 class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
1003     gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000,
1004                 maint_int=ArmPPI(num=25),
1005                 its=Gicv3Its(pio_addr=0x2e010000))
1006
1007     # Limiting to 128 since it will otherwise overlap with PCI space
1008     gic.cpu_max = 128
1009
1010     def _on_chip_devices(self):
1011         return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [
1012                 self.gic, self.gic.its
1013             ]
1014
1015     def setupBootLoader(self, cur_sys, loc):
1016         cur_sys.boot_loader = [ loc('boot_emm_v2.arm64') ]
1017         super(VExpress_GEM5_V2_Base,self).setupBootLoader(
1018                 cur_sys, loc)
1019
1020 class VExpress_GEM5_V2(VExpress_GEM5_V2_Base):
1021     hdlcd  = HDLcd(pxl_clk=VExpress_GEM5_V2_Base.dcc.osc_pxl,
1022                    pio_addr=0x2b000000, int_num=95)
1023
1024     def _on_chip_devices(self):
1025         return super(VExpress_GEM5_V2,self)._on_chip_devices() + [
1026                 self.hdlcd,
1027             ]