src/dev/arm/SMMUv3.py

   1 # Copyright (c) 2013, 2018-2020 ARM Limited
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  35
  36 from m5.params import *
  37 from m5.proxy import *
  38 from m5.util.fdthelper import *
  39 from m5.SimObject import *
  40 from m5.objects.ClockedObject import ClockedObject
  41
  42 class SMMUv3SlaveInterface(ClockedObject):
  43     type = 'SMMUv3SlaveInterface'
  44     cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'
  45
  46     slave = ResponsePort('Device port')
  47     ats_master = RequestPort('ATS master port')
  48     ats_slave  = ResponsePort('ATS slave port')
  49
  50     port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
  51     wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
  52     xlate_slots = Param.Unsigned(16, 'Translation slots')
  53
  54     utlb_entries = Param.Unsigned(32, 'Micro TLB size (entries)')
  55     utlb_assoc = Param.Unsigned(0, 'Micro TLB associativity (0=full)')
  56     utlb_policy = Param.String('rr', 'Micro TLB replacement policy')
  57     utlb_enable = Param.Bool(True, 'Micro TLB enable')
  58     utlb_lat = Param.Cycles(1, 'Micro TLB lookup latency')
  59     utlb_slots = Param.Cycles(1, 'Micro TLB lookup slots')
  60
  61     tlb_entries = Param.Unsigned(2048, 'Main TLB size (entries)')
  62     tlb_assoc = Param.Unsigned(4, 'Main TLB associativity (0=full)')
  63     tlb_policy = Param.String('rr', 'Main TLB replacement policy')
  64     tlb_enable = Param.Bool(True, 'Main TLB enable')
  65     tlb_lat = Param.Cycles(3, 'Main TLB lookup latency')
  66     tlb_slots = Param.Cycles(3, 'Main TLB lookup slots')
  67
  68     prefetch_enable = Param.Bool(False,
  69         'Enable prefetch')
  70     prefetch_reserve_last_way = Param.Bool(True,
  71         'Reserve last way of the main TLB for prefetched entries')
  72
  73 class SMMUv3(ClockedObject):
  74     type = 'SMMUv3'
  75     cxx_header = 'dev/arm/smmu_v3.hh'
  76
  77     master = RequestPort('Master port')
  78     master_walker = RequestPort(
  79         'Master port for SMMU initiated HWTW requests (optional)')
  80     control = ResponsePort(
  81         'Control port for accessing memory-mapped registers')
  82     sample_period = Param.Clock('10us', 'Stats sample period')
  83     reg_map = Param.AddrRange('Address range for control registers')
  84     system = Param.System(Parent.any, "System this device is part of")
  85
  86     slave_interfaces = VectorParam.SMMUv3SlaveInterface([], "Slave interfaces")
  87
  88     # SLAVE INTERFACE<->SMMU link parameters
  89     ifc_smmu_lat = Param.Cycles(8, 'IFC to SMMU communication latency')
  90     smmu_ifc_lat = Param.Cycles(8, 'SMMU to IFC communication latency')
  91
  92     # SMMU parameters
  93     xlate_slots = Param.Unsigned(64, 'SMMU translation slots')
  94     ptw_slots = Param.Unsigned(16, 'SMMU page table walk slots')
  95
  96     master_port_width = Param.Unsigned(16,
  97         'Master port width in bytes (= 1 beat)')
  98
  99     tlb_entries = Param.Unsigned(2048, 'TLB size (entries)')
 100     tlb_assoc = Param.Unsigned(4, 'TLB associativity (0=full)')
 101     tlb_policy = Param.String('rr', 'TLB replacement policy')
 102     tlb_enable = Param.Bool(False, 'TLB enable')
 103     tlb_lat = Param.Cycles(3, 'TLB lookup latency')
 104     tlb_slots = Param.Cycles(3, 'TLB lookup slots')
 105
 106     cfg_entries = Param.Unsigned(64, 'Config cache size (entries)')
 107     cfg_assoc = Param.Unsigned(4, 'Config cache associativity (0=full)')
 108     cfg_policy = Param.String('rr', 'Config cache replacement policy')
 109     cfg_enable = Param.Bool(True, 'Config cache enable')
 110     cfg_lat = Param.Cycles(3, 'Config cache lookup latency')
 111     cfg_slots = Param.Cycles(3, 'Config cache lookup slots')
 112
 113     ipa_entries = Param.Unsigned(128, 'IPA cache size (entries)')
 114     ipa_assoc = Param.Unsigned(4, 'IPA cache associativity (0=full)')
 115     ipa_policy = Param.String('rr', 'IPA cache replacement policy')
 116     ipa_enable = Param.Bool(False, 'IPA cache enable')
 117     ipa_lat = Param.Cycles(3, 'IPA cache lookup lantency')
 118     ipa_slots = Param.Cycles(3, 'IPA cache lookup slots')
 119
 120     walk_S1L0 = Param.Unsigned(4, 'Walk cache S1L0 size (entries)')
 121     walk_S1L1 = Param.Unsigned(28, 'Walk cache S1L1 size (entries)')
 122     walk_S1L2 = Param.Unsigned(348, 'Walk cache S1L2 size (entries)')
 123     walk_S1L3 = Param.Unsigned(4, 'Walk cache S1L3 size (entries)')
 124     walk_S2L0 = Param.Unsigned(4, 'Walk cache S2L0 size (entries)')
 125     walk_S2L1 = Param.Unsigned(28, 'Walk cache S2L1 size (entries)')
 126     walk_S2L2 = Param.Unsigned(92, 'Walk cache S2L2 size (entries)')
 127     walk_S2L3 = Param.Unsigned(4, 'Walk cache S2L3 size (entries)')
 128     walk_assoc = Param.Unsigned(4, 'Walk cache associativity (0=full)')
 129     walk_policy = Param.String('rr', 'Walk cache replacement policy')
 130     walk_enable = Param.Bool(True, 'Walk cache enable')
 131     wc_nonfinal_enable = Param.Bool(False,
 132         'Nonfinal translations use walk cache')
 133     wc_s1_levels = Param.Unsigned(7,
 134         'S1 PT levels cached in walk cache (bit 0 is L0, bit 1 is L1, etc)')
 135     wc_s2_levels = Param.Unsigned(7,
 136         'S2 PT levels cached in walk cache (bit 0 is L0, bit 1 is L1, etc)')
 137
 138     walk_lat   = Param.Cycles(4, 'Walk cache lookup latency')
 139     walk_slots = Param.Cycles(4, 'Walk cache lookup slots')
 140
 141     # [28:27] ST_LEVEL = 0b01, 2-level Stream Table supported in addition
 142     # to Linear Stream table.
 143     # [25:24] STALL_MODEL = 0b01, Stall is not supported, all faults
 144     # terminate transaction.
 145     # [22:21] TTENDIAN = 0b10, Endianness support for translation table walks
 146     # (0b10 = Little-endian).
 147     # [19] CD2L = 0b1, 2-level CD table supported.
 148     # [18] VMID16 = 0b1, 16-bit VMID supported.
 149     # [12] ASID16 = 0b1, 16-bit ASID supported.
 150     # [3:2] TTF = 0b10, Translation Table Formats (Stage 1/2)
 151     # (0b10 = AArch64).
 152     # [1] S1P = 0b1, Stage 1 translation supported.
 153     # [0] S2P = 0b1, Stage 2 translation supported.
 154     smmu_idr0 = Param.UInt32(0x094C100F, "SMMU_IDR0 register");
 155
 156     # [25:21] CMDQS = 0b00101, Maximum number of Command queue entries
 157     # as log 2 (entries) (0b00101 = 32 entries).
 158     smmu_idr1 = Param.UInt32(0x00A00000, "SMMU_IDR1 register");
 159
 160     smmu_idr2 = Param.UInt32(0, "SMMU_IDR2 register");
 161     smmu_idr3 = Param.UInt32(0, "SMMU_IDR3 register");
 162     smmu_idr4 = Param.UInt32(0, "SMMU_IDR4 register");
 163
 164     # [6] GRAN64K = 0b1, 64KB translation granule supported.
 165     # [4] GRAN4K = 0b1, 4KB translation granule supported.
 166     # [2:0] OAS = 0b101, Output Address Size (0b101 = 48-bit).
 167     smmu_idr5 = Param.UInt32(0x55, "SMMU_IDR5 register");
 168     smmu_iidr = Param.UInt32(0, "SMMU_IIDR register");
 169
 170     # [7:0] (0 = SMMUv3.0) (1 = SMMUv3.1)
 171     smmu_aidr = Param.UInt32(0, "SMMU_AIDR register");
 172
 173     def generateDeviceTree(self, state):
 174         reg_addr = self.reg_map.start
 175         reg_size = self.reg_map.size()
 176         node = FdtNode("smmuv3@%x" % long(reg_addr))
 177         node.appendCompatible("arm,smmu-v3")
 178         node.append(FdtPropertyWords("reg",
 179             state.addrCells(reg_addr) +
 180             state.sizeCells(reg_size)))
 181         node.append(FdtPropertyWords("#iommu-cells", [1]))
 182
 183         node.appendPhandle(self)
 184         yield node
 185
 186     def connect(self, device):
 187         """
 188         Helper method used to connect the SMMU. The master could
 189         be either a dma port (if the SMMU is attached directly to a
 190         dma device), or to a master port (this is the case where the SMMU
 191         is attached to a bridge).
 192         """
 193
 194         slave_interface = SMMUv3SlaveInterface()
 195
 196         if hasattr(device, "master"):
 197             slave_interface.slave = device.master
 198         elif hasattr(device, "dma"):
 199             slave_interface.slave = device.dma
 200         else:
 201             print("Unable to attach SMMUv3\n")
 202             sys.exit(1)
 203
 204         self.slave_interfaces.append(slave_interface)
 205
 206         # Storing a reference to the smmu to be used when generating
 207         # the binding in the device DTB.
 208         device._iommu = self