src/dev/arm/SMMUv3.py

   1 # Copyright (c) 2013, 2018-2019 ARM Limited
   2 # All rights reserved
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Redistribution and use in source and binary forms, with or without
  14 # modification, are permitted provided that the following conditions are
  15 # met: redistributions of source code must retain the above copyright
  16 # notice, this list of conditions and the following disclaimer;
  17 # redistributions in binary form must reproduce the above copyright
  18 # notice, this list of conditions and the following disclaimer in the
  19 # documentation and/or other materials provided with the distribution;
  20 # neither the name of the copyright holders nor the names of its
  21 # contributors may be used to endorse or promote products derived from
  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35
  36 from m5.params import *
  37 from m5.proxy import *
  38 from m5.util.fdthelper import *
  39 from m5.SimObject import *
  40 from m5.objects.ClockedObject import ClockedObject
  41
  42 class SMMUv3SlaveInterface(ClockedObject):
  43     type = 'SMMUv3SlaveInterface'
  44     cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'
  45
  46     slave = SlavePort('Device port')
  47     ats_master = MasterPort('ATS master port')
  48     ats_slave  = SlavePort('ATS slave port')
  49
  50     port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
  51     wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
  52     xlate_slots = Param.Unsigned(16, 'Translation slots')
  53
  54     utlb_entries = Param.Unsigned(32, 'Micro TLB size (entries)')
  55     utlb_assoc = Param.Unsigned(0, 'Micro TLB associativity (0=full)')
  56     utlb_policy = Param.String('rr', 'Micro TLB replacement policy')
  57     utlb_enable = Param.Bool(True, 'Micro TLB enable')
  58     utlb_lat = Param.Cycles(1, 'Micro TLB lookup latency')
  59     utlb_slots = Param.Cycles(1, 'Micro TLB lookup slots')
  60
  61     tlb_entries = Param.Unsigned(2048, 'Main TLB size (entries)')
  62     tlb_assoc = Param.Unsigned(4, 'Main TLB associativity (0=full)')
  63     tlb_policy = Param.String('rr', 'Main TLB replacement policy')
  64     tlb_enable = Param.Bool(True, 'Main TLB enable')
  65     tlb_lat = Param.Cycles(3, 'Main TLB lookup latency')
  66     tlb_slots = Param.Cycles(3, 'Main TLB lookup slots')
  67
  68     prefetch_enable = Param.Bool(False,
  69         'Enable prefetch')
  70     prefetch_reserve_last_way = Param.Bool(True,
  71         'Reserve last way of the main TLB for prefetched entries')
  72
  73 class SMMUv3(ClockedObject):
  74     type = 'SMMUv3'
  75     cxx_header = 'dev/arm/smmu_v3.hh'
  76
  77     master = MasterPort('Master port')
  78     master_walker = MasterPort(
  79         'Master port for SMMU initiated HWTW requests (optional)')
  80     control = SlavePort('Control port for accessing memory-mapped registers')
  81     sample_period = Param.Clock('10us', 'Stats sample period')
  82     reg_map = Param.AddrRange('Address range for control registers')
  83     system = Param.System(Parent.any, "System this device is part of")
  84
  85     slave_interfaces = VectorParam.SMMUv3SlaveInterface([], "Slave interfaces")
  86
  87     # SLAVE INTERFACE<->SMMU link parameters
  88     ifc_smmu_lat = Param.Cycles(8, 'IFC to SMMU communication latency')
  89     smmu_ifc_lat = Param.Cycles(8, 'SMMU to IFC communication latency')
  90
  91     # SMMU parameters
  92     xlate_slots = Param.Unsigned(64, 'SMMU translation slots')
  93     ptw_slots = Param.Unsigned(16, 'SMMU page table walk slots')
  94
  95     master_port_width = Param.Unsigned(16,
  96         'Master port width in bytes (= 1 beat)')
  97
  98     tlb_entries = Param.Unsigned(2048, 'TLB size (entries)')
  99     tlb_assoc = Param.Unsigned(4, 'TLB associativity (0=full)')
 100     tlb_policy = Param.String('rr', 'TLB replacement policy')
 101     tlb_enable = Param.Bool(False, 'TLB enable')
 102     tlb_lat = Param.Cycles(3, 'TLB lookup latency')
 103     tlb_slots = Param.Cycles(3, 'TLB lookup slots')
 104
 105     cfg_entries = Param.Unsigned(64, 'Config cache size (entries)')
 106     cfg_assoc = Param.Unsigned(4, 'Config cache associativity (0=full)')
 107     cfg_policy = Param.String('rr', 'Config cache replacement policy')
 108     cfg_enable = Param.Bool(True, 'Config cache enable')
 109     cfg_lat = Param.Cycles(3, 'Config cache lookup latency')
 110     cfg_slots = Param.Cycles(3, 'Config cache lookup slots')
 111
 112     ipa_entries = Param.Unsigned(128, 'IPA cache size (entries)')
 113     ipa_assoc = Param.Unsigned(4, 'IPA cache associativity (0=full)')
 114     ipa_policy = Param.String('rr', 'IPA cache replacement policy')
 115     ipa_enable = Param.Bool(False, 'IPA cache enable')
 116     ipa_lat = Param.Cycles(3, 'IPA cache lookup lantency')
 117     ipa_slots = Param.Cycles(3, 'IPA cache lookup slots')
 118
 119     walk_S1L0 = Param.Unsigned(4, 'Walk cache S1L0 size (entries)')
 120     walk_S1L1 = Param.Unsigned(28, 'Walk cache S1L1 size (entries)')
 121     walk_S1L2 = Param.Unsigned(348, 'Walk cache S1L2 size (entries)')
 122     walk_S1L3 = Param.Unsigned(4, 'Walk cache S1L3 size (entries)')
 123     walk_S2L0 = Param.Unsigned(4, 'Walk cache S2L0 size (entries)')
 124     walk_S2L1 = Param.Unsigned(28, 'Walk cache S2L1 size (entries)')
 125     walk_S2L2 = Param.Unsigned(92, 'Walk cache S2L2 size (entries)')
 126     walk_S2L3 = Param.Unsigned(4, 'Walk cache S2L3 size (entries)')
 127     walk_assoc = Param.Unsigned(4, 'Walk cache associativity (0=full)')
 128     walk_policy = Param.String('rr', 'Walk cache replacement policy')
 129     walk_enable = Param.Bool(True, 'Walk cache enable')
 130     wc_nonfinal_enable = Param.Bool(False,
 131         'Nonfinal translations use walk cache')
 132     wc_s1_levels = Param.Unsigned(7,
 133         'S1 PT levels cached in walk cache (bit 0 is L0, bit 1 is L1, etc)')
 134     wc_s2_levels = Param.Unsigned(7,
 135         'S2 PT levels cached in walk cache (bit 0 is L0, bit 1 is L1, etc)')
 136
 137     walk_lat   = Param.Cycles(4, 'Walk cache lookup latency')
 138     walk_slots = Param.Cycles(4, 'Walk cache lookup slots')
 139
 140     # [28:27] ST_LEVEL = 0b01, 2-level Stream Table supported in addition
 141     # to Linear Stream table.
 142     # [25:24] STALL_MODEL = 0b01, Stall is not supported, all faults
 143     # terminate transaction.
 144     # [22:21] TTENDIAN = 0b10, Endianness support for translation table walks
 145     # (0b10 = Little-endian).
 146     # [19] CD2L = 0b1, 2-level CD table supported.
 147     # [18] VMID16 = 0b1, 16-bit VMID supported.
 148     # [12] ASID16 = 0b1, 16-bit ASID supported.
 149     # [3:2] TTF = 0b10, Translation Table Formats (Stage 1/2)
 150     # (0b10 = AArch64).
 151     # [1] S1P = 0b1, Stage 1 translation supported.
 152     # [0] S2P = 0b1, Stage 2 translation supported.
 153     smmu_idr0 = Param.UInt32(0x094C100F, "SMMU_IDR0 register");
 154
 155     # [25:21] CMDQS = 0b00101, Maximum number of Command queue entries
 156     # as log 2 (entries) (0b00101 = 32 entries).
 157     smmu_idr1 = Param.UInt32(0x00A00000, "SMMU_IDR1 register");
 158
 159     smmu_idr2 = Param.UInt32(0, "SMMU_IDR2 register");
 160     smmu_idr3 = Param.UInt32(0, "SMMU_IDR3 register");
 161     smmu_idr4 = Param.UInt32(0, "SMMU_IDR4 register");
 162
 163     # [6] GRAN64K = 0b1, 64KB translation granule supported.
 164     # [4] GRAN4K = 0b1, 4KB translation granule supported.
 165     # [2:0] OAS = 0b101, Output Address Size (0b101 = 48-bit).
 166     smmu_idr5 = Param.UInt32(0x55, "SMMU_IDR5 register");
 167     smmu_iidr = Param.UInt32(0, "SMMU_IIDR register");
 168
 169     # [7:0] (0 = SMMUv3.0) (1 = SMMUv3.1)
 170     smmu_aidr = Param.UInt32(0, "SMMU_AIDR register");
 171
 172     def generateDeviceTree(self, state):
 173         reg_addr = self.reg_map.start
 174         reg_size = self.reg_map.size()
 175         node = FdtNode("smmuv3@%x" % long(reg_addr))
 176         node.appendCompatible("arm,smmu-v3")
 177         node.append(FdtPropertyWords("reg",
 178             state.addrCells(reg_addr) +
 179             state.sizeCells(reg_size)))
 180         node.append(FdtPropertyWords("#iommu-cells", [1]))
 181
 182         node.appendPhandle(self)
 183         yield node
 184
 185     def connect(self, device, bus):
 186         """
 187         Helper method used to connect the SMMU. The master could
 188         be either a dma port (if the SMMU is attached directly to a
 189         dma device), or to a master port (this is the case where the SMMU
 190         is attached to a bridge).
 191         """
 192
 193         self.master = bus.slave
 194         self.control = bus.master
 195
 196         slave_interface = SMMUv3SlaveInterface()
 197
 198         if hasattr(device, "master"):
 199             slave_interface.slave = device.master
 200         elif hasattr(device, "dma"):
 201             slave_interface.slave = device.dma
 202         else:
 203             print("Unable to attach SMMUv3\n")
 204             sys.exit(1)
 205
 206         self.slave_interfaces.append(slave_interface)
 207
 208         # Storing a reference to the smmu to be used when generating
 209         # the binding in the device DTB.
 210         device._iommu = self