src/dev/arm/base_gic.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2017-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Andreas Sandberg
  38  */
  39
  40 /** @file
  41  * Base class for ARM GIC implementations
  42  */
  43
  44 #ifndef __DEV_ARM_BASE_GIC_H__
  45 #define __DEV_ARM_BASE_GIC_H__
  46
  47 #include <unordered_map>
  48
  49 #include "arch/arm/system.hh"
  50 #include "dev/io_device.hh"
  51
  52 class Platform;
  53 class RealView;
  54 class ThreadContext;
  55 class ArmInterruptPin;
  56 class ArmSPI;
  57 class ArmPPI;
  58
  59 struct ArmInterruptPinParams;
  60 struct ArmPPIParams;
  61 struct ArmSPIParams;
  62 struct BaseGicParams;
  63
  64 class BaseGic :  public PioDevice
  65 {
  66   public:
  67     typedef BaseGicParams Params;
  68
  69     BaseGic(const Params *p);
  70     virtual ~BaseGic();
  71     void init() override;
  72
  73     const Params * params() const;
  74
  75     /**
  76      * Post an interrupt from a device that is connected to the GIC.
  77      *
  78      * Depending on the configuration, the GIC will pass this interrupt
  79      * on through to a CPU.
  80      *
  81      * @param num number of interrupt to send
  82      */
  83     virtual void sendInt(uint32_t num) = 0;
  84
  85     /**
  86      * Interface call for private peripheral interrupts.
  87      *
  88      * @param num number of interrupt to send
  89      * @param cpu CPU to forward interrupt to
  90      */
  91     virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
  92     virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
  93
  94     /**
  95      * Clear an interrupt from a device that is connected to the GIC.
  96      *
  97      * Depending on the configuration, the GIC may de-assert it's CPU
  98      * line.
  99      *
 100      * @param num number of interrupt to send
 101      */
 102     virtual void clearInt(uint32_t num) = 0;
 103
 104     ArmSystem *
 105     getSystem() const
 106     {
 107         return (ArmSystem *) sys;
 108     }
 109
 110   protected:
 111     /** Platform this GIC belongs to. */
 112     Platform *platform;
 113 };
 114
 115 class BaseGicRegisters
 116 {
 117   public:
 118     virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
 119     virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
 120
 121     virtual void writeDistributor(ContextID ctx, Addr daddr,
 122                                   uint32_t data) = 0;
 123     virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
 124 };
 125
 126 /**
 127  * This SimObject is instantiated in the python world and
 128  * serves as an ArmInterruptPin generator. In this way it
 129  * is possible to instantiate a single generator per component
 130  * during configuration, and to dynamically spawn ArmInterruptPins.
 131  * See ArmPPIGen for more info on how this is used.
 132  */
 133 class ArmInterruptPinGen : public SimObject
 134 {
 135   public:
 136     ArmInterruptPinGen(const ArmInterruptPinParams *p);
 137
 138     virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
 139 };
 140
 141 /**
 142  * Shared Peripheral Interrupt Generator
 143  * It is capable of generating one interrupt only: it maintains a pointer
 144  * to it and returns it every time it is asked for it (via the get metod)
 145  */
 146 class ArmSPIGen : public ArmInterruptPinGen
 147 {
 148   public:
 149     ArmSPIGen(const ArmSPIParams *p);
 150
 151     ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
 152   protected:
 153     ArmSPI* pin;
 154 };
 155
 156 /**
 157  * Private Peripheral Interrupt Generator
 158  * Since PPIs are banked in the GIC, this class is capable of generating
 159  * more than one interrupt (one per ContextID).
 160  */
 161 class ArmPPIGen : public ArmInterruptPinGen
 162 {
 163   public:
 164     ArmPPIGen(const ArmPPIParams *p);
 165
 166     ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
 167   protected:
 168     std::unordered_map<ContextID, ArmPPI*> pins;
 169 };
 170
 171 /**
 172  * Generic representation of an Arm interrupt pin.
 173  */
 174 class ArmInterruptPin
 175 {
 176     friend class ArmInterruptPinGen;
 177   protected:
 178     ArmInterruptPin(Platform *platform, ThreadContext *tc,
 179                     uint32_t int_num);
 180
 181   public: /* Public interface */
 182     /**
 183      * Set the thread context owning this interrupt.
 184      *
 185      * This method is used to set the thread context for interrupts
 186      * that are thread/CPU-specific. Only devices that are used in
 187      * such a context are expected to call this method.
 188      */
 189     void setThreadContext(ThreadContext *tc);
 190
 191     /** Get interrupt number */
 192     uint32_t num() const { return intNum; }
 193
 194     /** Signal an interrupt */
 195     virtual void raise() = 0;
 196     /** Clear a signalled interrupt */
 197     virtual void clear() = 0;
 198
 199   protected:
 200     /**
 201      * Get the target context ID of this interrupt.
 202      *
 203      * @pre setThreadContext() must have been called prior to calling
 204      * this method.
 205      */
 206     ContextID targetContext() const;
 207
 208     /**
 209      * Pointer to the thread context that owns this interrupt in case
 210      * it is a thread-/CPU-private interrupt
 211      */
 212     const ThreadContext *threadContext;
 213
 214     /** Arm platform to use for interrupt generation */
 215     RealView *const platform;
 216
 217     /** Interrupt number to generate */
 218     const uint32_t intNum;
 219 };
 220
 221 class ArmSPI : public ArmInterruptPin
 222 {
 223     friend class ArmSPIGen;
 224   private:
 225     ArmSPI(Platform *platform, uint32_t int_num);
 226
 227   public:
 228     void raise() override;
 229     void clear() override;
 230 };
 231
 232 class ArmPPI : public ArmInterruptPin
 233 {
 234     friend class ArmPPIGen;
 235   private:
 236     ArmPPI(Platform *platform, ThreadContext *tc, uint32_t int_num);
 237
 238   public:
 239     void raise() override;
 240     void clear() override;
 241 };
 242
 243 #endif