2 * Copyright (c) 2013-2015 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Rene de Jong
39 #ifndef __DEV_ARM_FLASH_DEVICE_HH__
40 #define __DEV_ARM_FLASH_DEVICE_HH__
44 #include "base/statistics.hh"
45 #include "debug/FlashDevice.hh"
46 #include "dev/arm/abstract_nvm.hh"
47 #include "enums/DataDistribution.hh"
48 #include "params/FlashDevice.hh"
49 #include "sim/serialize.hh"
53 * The Flash Device model is a timing model for a NAND flash device.
54 * It doesn't tranfer any data
56 class FlashDevice : public AbstractNVM
60 /** Initialize functions*/
61 FlashDevice(const FlashDeviceParams*);
64 /** Checkpoint functions*/
65 DrainState drain() override;
68 void serialize(CheckpointOut &cp) const override;
69 void unserialize(CheckpointIn &cp) override;
72 /** Defines the possible actions to the flash*/
78 * A copy involves taking all the used pages from a block and store
84 /** Every logical address maps to a physical block and a physical page*/
90 struct CallBackEntry {
95 struct FlashDeviceStats {
96 /** Amount of GC activations*/
97 Stats::Scalar totalGCActivations;
99 /** Histogram of address accesses*/
100 Stats::Histogram writeAccess;
101 Stats::Histogram readAccess;
102 Stats::Histogram fileSystemAccess;
104 /** Histogram of access latencies*/
105 Stats::Histogram writeLatency;
106 Stats::Histogram readLatency;
109 /** Device access functions Inherrited from AbstractNVM*/
110 void initializeMemory(uint64_t disk_size, uint32_t sector_size) override
112 initializeFlash(disk_size, sector_size);
115 void readMemory(uint64_t address, uint32_t amount,
116 Callback *event) override
118 accessDevice(address, amount, event, ActionRead);
121 void writeMemory(uint64_t address, uint32_t amount,
122 Callback *event) override
124 accessDevice(address, amount, event, ActionWrite);
127 /**Initialization function; called when all disk specifics are known*/
128 void initializeFlash(uint64_t disk_size, uint32_t sector_size);
130 /**Flash action function*/
131 void accessDevice(uint64_t address, uint32_t amount, Callback *event,
134 /** Event rescheduler*/
135 void actionComplete();
137 /** FTL functionality */
138 Tick remap(uint64_t logic_page_addr);
140 /** Access time calculator*/
141 Tick accessTimes(uint64_t address, Actions accesstype);
143 /** Function to indicate that a page is known*/
144 void clearUnknownPages(uint32_t index);
146 /** Function to test if a page is known*/
147 bool getUnknownPages(uint32_t index);
149 /**Stats register function*/
150 void regStats() override;
152 /** Disk sizes in bytes */
154 const uint32_t blockSize;
155 const uint32_t pageSize;
157 /** Garbage collection algorithm emulator */
158 const uint32_t GCActivePercentage;
160 /** Access latencies */
161 const Tick readLatency;
162 const Tick writeLatency;
163 const Tick eraseLatency;
165 /** Flash organization */
166 const Enums::DataDistribution dataDistribution;
167 const uint32_t numPlanes;
169 /** RequestHandler stats */
170 struct FlashDeviceStats stats;
172 /** Disk dimensions in pages and blocks */
173 uint32_t pagesPerBlock;
174 uint32_t pagesPerDisk;
175 uint32_t blocksPerDisk;
180 * when the disk is first started we are unsure of the number of
181 * used pages, this variable will help determining what we do know.
183 std::vector<uint32_t> unknownPages;
184 /** address to logic place has a block and a page field*/
185 std::vector<struct PageMapEntry> locationTable;
186 /** number of valid entries per block*/
187 std::vector<uint32_t> blockValidEntries;
188 /** number of empty entries*/
189 std::vector<uint32_t> blockEmptyEntries;
191 /**This vector of queues keeps track of all the callbacks per plane*/
192 std::vector<std::deque<struct CallBackEntry> > planeEventQueue;
194 /** Completion event */
195 EventFunctionWrapper planeEvent;
197 #endif //__DEV_ARM_FLASH_DEVICE_HH__