2 * Copyright (c) 2013, 2015 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Giacomo Gabrielli
41 #include "dev/arm/generic_timer.hh"
43 #include "arch/arm/system.hh"
44 #include "debug/Timer.hh"
45 #include "dev/arm/base_gic.hh"
46 #include "mem/packet_access.hh"
47 #include "params/GenericTimer.hh"
48 #include "params/GenericTimerMem.hh"
50 SystemCounter::SystemCounter()
51 : _freq(0), _period(0), _resetTick(0), _regCntkctl(0)
57 SystemCounter::setFreq(uint32_t freq
)
60 // Altering the frequency after boot shouldn't be done in practice.
61 warn_once("The frequency of the system counter has already been set");
64 _period
= (1.0 / freq
) * SimClock::Frequency
;
65 _resetTick
= curTick();
69 SystemCounter::serialize(CheckpointOut
&cp
) const
71 SERIALIZE_SCALAR(_regCntkctl
);
72 SERIALIZE_SCALAR(_freq
);
73 SERIALIZE_SCALAR(_period
);
74 SERIALIZE_SCALAR(_resetTick
);
78 SystemCounter::unserialize(CheckpointIn
&cp
)
80 // We didn't handle CNTKCTL in this class before, assume it's zero
81 // if it isn't present.
82 if (!UNSERIALIZE_OPT_SCALAR(_regCntkctl
))
84 UNSERIALIZE_SCALAR(_freq
);
85 UNSERIALIZE_SCALAR(_period
);
86 UNSERIALIZE_SCALAR(_resetTick
);
91 ArchTimer::ArchTimer(const std::string
&name
,
93 SystemCounter
&sysctr
,
94 const Interrupt
&interrupt
)
95 : _name(name
), _parent(parent
), _systemCounter(sysctr
),
96 _interrupt(interrupt
),
97 _control(0), _counterLimit(0), _offset(0),
98 _counterLimitReachedEvent(this)
103 ArchTimer::counterLimitReached()
105 _control
.istatus
= 1;
107 if (!_control
.enable
)
110 DPRINTF(Timer
, "Counter limit reached\n");
111 if (!_control
.imask
) {
112 DPRINTF(Timer
, "Causing interrupt\n");
118 ArchTimer::updateCounter()
120 if (_counterLimitReachedEvent
.scheduled())
121 _parent
.deschedule(_counterLimitReachedEvent
);
122 if (value() >= _counterLimit
) {
123 counterLimitReached();
125 const auto period(_systemCounter
.period());
126 _control
.istatus
= 0;
127 _parent
.schedule(_counterLimitReachedEvent
,
128 curTick() + (_counterLimit
- value()) * period
);
133 ArchTimer::setCompareValue(uint64_t val
)
140 ArchTimer::setTimerValue(uint32_t val
)
142 setCompareValue(value() + sext
<32>(val
));
146 ArchTimer::setControl(uint32_t val
)
148 ArchTimerCtrl new_ctl
= val
;
149 if ((new_ctl
.enable
&& !new_ctl
.imask
) &&
150 !(_control
.enable
&& !_control
.imask
)) {
151 // Re-evalute the timer condition
152 if (_counterLimit
>= value()) {
153 _control
.istatus
= 1;
155 DPRINTF(Timer
, "Causing interrupt in control\n");
159 _control
.enable
= new_ctl
.enable
;
160 _control
.imask
= new_ctl
.imask
;
164 ArchTimer::setOffset(uint64_t val
)
171 ArchTimer::value() const
173 return _systemCounter
.value() - _offset
;
177 ArchTimer::serialize(CheckpointOut
&cp
) const
179 paramOut(cp
, "control_serial", _control
);
180 SERIALIZE_SCALAR(_counterLimit
);
181 SERIALIZE_SCALAR(_offset
);
183 const bool event_scheduled(_counterLimitReachedEvent
.scheduled());
184 SERIALIZE_SCALAR(event_scheduled
);
185 if (event_scheduled
) {
186 const Tick
event_time(_counterLimitReachedEvent
.when());
187 SERIALIZE_SCALAR(event_time
);
192 ArchTimer::unserialize(CheckpointIn
&cp
)
194 paramIn(cp
, "control_serial", _control
);
195 // We didn't serialize an offset before we added support for the
196 // virtual timer. Consider it optional to maintain backwards
198 if (!UNSERIALIZE_OPT_SCALAR(_offset
))
200 bool event_scheduled
;
201 UNSERIALIZE_SCALAR(event_scheduled
);
202 if (event_scheduled
) {
204 UNSERIALIZE_SCALAR(event_time
);
205 _parent
.schedule(_counterLimitReachedEvent
, event_time
);
210 ArchTimer::Interrupt::send()
213 _gic
.sendPPInt(_irq
, _cpu
);
221 ArchTimer::Interrupt::clear()
224 _gic
.clearPPInt(_irq
, _cpu
);
231 GenericTimer::GenericTimer(GenericTimerParams
*p
)
234 irqPhys(p
->int_phys
),
237 dynamic_cast<ArmSystem
&>(*p
->system
).setGenericTimer(this);
241 GenericTimer::serialize(CheckpointOut
&cp
) const
243 paramOut(cp
, "cpu_count", timers
.size());
245 systemCounter
.serializeSection(cp
, "sys_counter");
247 for (int i
= 0; i
< timers
.size(); ++i
) {
248 const CoreTimers
&core(*timers
[i
]);
250 // This should really be phys_timerN, but we are stuck with
251 // arch_timer for backwards compatibility.
252 core
.phys
.serializeSection(cp
, csprintf("arch_timer%d", i
));
253 core
.virt
.serializeSection(cp
, csprintf("virt_timer%d", i
));
258 GenericTimer::unserialize(CheckpointIn
&cp
)
260 systemCounter
.unserializeSection(cp
, "sys_counter");
262 // Try to unserialize the CPU count. Old versions of the timer
263 // model assumed a 8 CPUs, so we fall back to that if the field
265 static const unsigned OLD_CPU_MAX
= 8;
267 if (!UNSERIALIZE_OPT_SCALAR(cpu_count
)) {
268 warn("Checkpoint does not contain CPU count, assuming %i CPUs\n",
270 cpu_count
= OLD_CPU_MAX
;
273 for (int i
= 0; i
< cpu_count
; ++i
) {
274 CoreTimers
&core(getTimers(i
));
275 // This should really be phys_timerN, but we are stuck with
276 // arch_timer for backwards compatibility.
277 core
.phys
.unserializeSection(cp
, csprintf("arch_timer%d", i
));
278 core
.virt
.unserializeSection(cp
, csprintf("virt_timer%d", i
));
283 GenericTimer::CoreTimers
&
284 GenericTimer::getTimers(int cpu_id
)
286 if (cpu_id
>= timers
.size())
287 createTimers(cpu_id
+ 1);
289 return *timers
[cpu_id
];
293 GenericTimer::createTimers(unsigned cpus
)
295 assert(timers
.size() < cpus
);
297 const unsigned old_cpu_count(timers
.size());
299 for (unsigned i
= old_cpu_count
; i
< cpus
; ++i
) {
301 new CoreTimers(*this, i
, irqPhys
, irqVirt
));
307 GenericTimer::setMiscReg(int reg
, unsigned cpu
, MiscReg val
)
309 CoreTimers
&core(getTimers(cpu
));
313 case MISCREG_CNTFRQ_EL0
:
314 systemCounter
.setFreq(val
);
317 case MISCREG_CNTKCTL
:
318 case MISCREG_CNTKCTL_EL1
:
319 systemCounter
.setKernelControl(val
);
323 case MISCREG_CNTP_CVAL
:
324 case MISCREG_CNTP_CVAL_NS
:
325 case MISCREG_CNTP_CVAL_EL0
:
326 core
.phys
.setCompareValue(val
);
329 case MISCREG_CNTP_TVAL
:
330 case MISCREG_CNTP_TVAL_NS
:
331 case MISCREG_CNTP_TVAL_EL0
:
332 core
.phys
.setTimerValue(val
);
335 case MISCREG_CNTP_CTL
:
336 case MISCREG_CNTP_CTL_NS
:
337 case MISCREG_CNTP_CTL_EL0
:
338 core
.phys
.setControl(val
);
343 case MISCREG_CNTPCT_EL0
:
345 case MISCREG_CNTVCT_EL0
:
346 warn("Ignoring write to read only count register: %s\n",
351 case MISCREG_CNTVOFF
:
352 case MISCREG_CNTVOFF_EL2
:
353 core
.virt
.setOffset(val
);
356 case MISCREG_CNTV_CVAL
:
357 case MISCREG_CNTV_CVAL_EL0
:
358 core
.virt
.setCompareValue(val
);
361 case MISCREG_CNTV_TVAL
:
362 case MISCREG_CNTV_TVAL_EL0
:
363 core
.virt
.setTimerValue(val
);
366 case MISCREG_CNTV_CTL
:
367 case MISCREG_CNTV_CTL_EL0
:
368 core
.virt
.setControl(val
);
371 // PL1 phys. timer, secure
372 case MISCREG_CNTP_CTL_S
:
373 case MISCREG_CNTPS_CVAL_EL1
:
374 case MISCREG_CNTPS_TVAL_EL1
:
375 case MISCREG_CNTPS_CTL_EL1
:
378 // PL2 phys. timer, non-secure
379 case MISCREG_CNTHCTL
:
380 case MISCREG_CNTHCTL_EL2
:
381 case MISCREG_CNTHP_CVAL
:
382 case MISCREG_CNTHP_CVAL_EL2
:
383 case MISCREG_CNTHP_TVAL
:
384 case MISCREG_CNTHP_TVAL_EL2
:
385 case MISCREG_CNTHP_CTL
:
386 case MISCREG_CNTHP_CTL_EL2
:
387 warn("Writing to unimplemented register: %s\n",
392 warn("Writing to unknown register: %s\n", miscRegName
[reg
]);
399 GenericTimer::readMiscReg(int reg
, unsigned cpu
)
401 CoreTimers
&core(getTimers(cpu
));
405 case MISCREG_CNTFRQ_EL0
:
406 return systemCounter
.freq();
408 case MISCREG_CNTKCTL
:
409 case MISCREG_CNTKCTL_EL1
:
410 return systemCounter
.getKernelControl();
413 case MISCREG_CNTP_CVAL
:
414 case MISCREG_CNTP_CVAL_EL0
:
415 return core
.phys
.compareValue();
417 case MISCREG_CNTP_TVAL
:
418 case MISCREG_CNTP_TVAL_EL0
:
419 return core
.phys
.timerValue();
421 case MISCREG_CNTP_CTL
:
422 case MISCREG_CNTP_CTL_EL0
:
423 case MISCREG_CNTP_CTL_NS
:
424 return core
.phys
.control();
427 case MISCREG_CNTPCT_EL0
:
428 return core
.phys
.value();
433 case MISCREG_CNTVCT_EL0
:
434 return core
.virt
.value();
436 case MISCREG_CNTVOFF
:
437 case MISCREG_CNTVOFF_EL2
:
438 return core
.virt
.offset();
440 case MISCREG_CNTV_CVAL
:
441 case MISCREG_CNTV_CVAL_EL0
:
442 return core
.virt
.compareValue();
444 case MISCREG_CNTV_TVAL
:
445 case MISCREG_CNTV_TVAL_EL0
:
446 return core
.virt
.timerValue();
448 case MISCREG_CNTV_CTL
:
449 case MISCREG_CNTV_CTL_EL0
:
450 return core
.virt
.control();
452 // PL1 phys. timer, secure
453 case MISCREG_CNTP_CTL_S
:
454 case MISCREG_CNTPS_CVAL_EL1
:
455 case MISCREG_CNTPS_TVAL_EL1
:
456 case MISCREG_CNTPS_CTL_EL1
:
459 // PL2 phys. timer, non-secure
460 case MISCREG_CNTHCTL
:
461 case MISCREG_CNTHCTL_EL2
:
462 case MISCREG_CNTHP_CVAL
:
463 case MISCREG_CNTHP_CVAL_EL2
:
464 case MISCREG_CNTHP_TVAL
:
465 case MISCREG_CNTHP_TVAL_EL2
:
466 case MISCREG_CNTHP_CTL
:
467 case MISCREG_CNTHP_CTL_EL2
:
468 warn("Reading from unimplemented register: %s\n",
474 warn("Reading from unknown register: %s\n", miscRegName
[reg
]);
481 GenericTimerMem::GenericTimerMem(GenericTimerMemParams
*p
)
483 ctrlRange(RangeSize(p
->base
, TheISA::PageBytes
)),
484 timerRange(RangeSize(p
->base
+ TheISA::PageBytes
, TheISA::PageBytes
)),
485 addrRanges
{ctrlRange
, timerRange
},
487 physTimer(csprintf("%s.phys_timer0", name()),
488 *this, systemCounter
,
489 ArchTimer::Interrupt(*p
->gic
, p
->int_phys
)),
490 virtTimer(csprintf("%s.virt_timer0", name()),
491 *this, systemCounter
,
492 ArchTimer::Interrupt(*p
->gic
, p
->int_virt
))
497 GenericTimerMem::serialize(CheckpointOut
&cp
) const
499 paramOut(cp
, "timer_count", 1);
501 systemCounter
.serializeSection(cp
, "sys_counter");
503 physTimer
.serializeSection(cp
, "phys_timer0");
504 virtTimer
.serializeSection(cp
, "virt_timer0");
508 GenericTimerMem::unserialize(CheckpointIn
&cp
)
510 systemCounter
.unserializeSection(cp
, "sys_counter");
512 unsigned timer_count
;
513 UNSERIALIZE_SCALAR(timer_count
);
514 // The timer count variable is just here for future versions where
515 // we support more than one set of timers.
516 if (timer_count
!= 1)
517 panic("Incompatible checkpoint: Only one set of timers supported");
519 physTimer
.unserializeSection(cp
, "phys_timer0");
520 virtTimer
.unserializeSection(cp
, "virt_timer0");
524 GenericTimerMem::read(PacketPtr pkt
)
526 const unsigned size(pkt
->getSize());
527 const Addr
addr(pkt
->getAddr());
531 if (ctrlRange
.contains(addr
)) {
532 value
= ctrlRead(addr
- ctrlRange
.start(), size
);
533 } else if (timerRange
.contains(addr
)) {
534 value
= timerRead(addr
- timerRange
.start(), size
);
536 panic("Invalid address: 0x%x\n", addr
);
539 DPRINTF(Timer
, "Read 0x%x <- 0x%x(%i)\n", value
, addr
, size
);
542 pkt
->set
<uint64_t>(value
);
543 } else if (size
== 4) {
544 pkt
->set
<uint32_t>(value
);
546 panic("Unexpected access size: %i\n", size
);
553 GenericTimerMem::write(PacketPtr pkt
)
555 const unsigned size(pkt
->getSize());
556 if (size
!= 8 && size
!= 4)
557 panic("Unexpected access size\n");
559 const Addr
addr(pkt
->getAddr());
560 const uint64_t value(size
== 8 ?
561 pkt
->get
<uint64_t>() : pkt
->get
<uint32_t>());
563 DPRINTF(Timer
, "Write 0x%x -> 0x%x(%i)\n", value
, addr
, size
);
564 if (ctrlRange
.contains(addr
)) {
565 ctrlWrite(addr
- ctrlRange
.start(), size
, value
);
566 } else if (timerRange
.contains(addr
)) {
567 timerWrite(addr
- timerRange
.start(), size
, value
);
569 panic("Invalid address: 0x%x\n", addr
);
577 GenericTimerMem::ctrlRead(Addr addr
, size_t size
) const
582 return systemCounter
.freq();
585 return 0x3; // Frame 0 implemented with virtual timers
588 case CTRL_CNTACR_BASE
:
589 warn("Reading from unimplemented control register (0x%x)\n", addr
);
592 case CTRL_CNTVOFF_LO_BASE
:
593 return virtTimer
.offset();
595 case CTRL_CNTVOFF_HI_BASE
:
596 return virtTimer
.offset() >> 32;
599 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr
, size
);
602 } else if (size
== 8) {
604 case CTRL_CNTVOFF_LO_BASE
:
605 return virtTimer
.offset();
608 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr
, size
);
612 panic("Invalid access size: %i\n", size
);
617 GenericTimerMem::ctrlWrite(Addr addr
, size_t size
, uint64_t value
)
624 case CTRL_CNTACR_BASE
:
625 warn("Write to unimplemented control register (0x%x)\n", addr
);
628 case CTRL_CNTVOFF_LO_BASE
:
630 insertBits(virtTimer
.offset(), 31, 0, value
));
633 case CTRL_CNTVOFF_HI_BASE
:
635 insertBits(virtTimer
.offset(), 63, 32, value
));
639 warn("Ignoring write to unexpected address (0x%x:%i)\n",
643 } else if (size
== 8) {
645 case CTRL_CNTVOFF_LO_BASE
:
646 virtTimer
.setOffset(value
);
650 warn("Ignoring write to unexpected address (0x%x:%i)\n",
655 panic("Invalid access size: %i\n", size
);
660 GenericTimerMem::timerRead(Addr addr
, size_t size
) const
664 case TIMER_CNTPCT_LO
:
665 return physTimer
.value();
667 case TIMER_CNTPCT_HI
:
668 return physTimer
.value() >> 32;
670 case TIMER_CNTVCT_LO
:
671 return virtTimer
.value();
673 case TIMER_CNTVCT_HI
:
674 return virtTimer
.value() >> 32;
677 return systemCounter
.freq();
679 case TIMER_CNTEL0ACR
:
680 warn("Read from unimplemented timer register (0x%x)\n", addr
);
683 case CTRL_CNTVOFF_LO_BASE
:
684 return virtTimer
.offset();
686 case CTRL_CNTVOFF_HI_BASE
:
687 return virtTimer
.offset() >> 32;
689 case TIMER_CNTP_CVAL_LO
:
690 return physTimer
.compareValue();
692 case TIMER_CNTP_CVAL_HI
:
693 return physTimer
.compareValue() >> 32;
695 case TIMER_CNTP_TVAL
:
696 return physTimer
.timerValue();
699 return physTimer
.control();
701 case TIMER_CNTV_CVAL_LO
:
702 return virtTimer
.compareValue();
704 case TIMER_CNTV_CVAL_HI
:
705 return virtTimer
.compareValue() >> 32;
707 case TIMER_CNTV_TVAL
:
708 return virtTimer
.timerValue();
711 return virtTimer
.control();
714 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr
, size
);
717 } else if (size
== 8) {
719 case TIMER_CNTPCT_LO
:
720 return physTimer
.value();
722 case TIMER_CNTVCT_LO
:
723 return virtTimer
.value();
725 case CTRL_CNTVOFF_LO_BASE
:
726 return virtTimer
.offset();
728 case TIMER_CNTP_CVAL_LO
:
729 return physTimer
.compareValue();
731 case TIMER_CNTV_CVAL_LO
:
732 return virtTimer
.compareValue();
735 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr
, size
);
739 panic("Invalid access size: %i\n", size
);
744 GenericTimerMem::timerWrite(Addr addr
, size_t size
, uint64_t value
)
748 case TIMER_CNTEL0ACR
:
749 warn("Unimplemented timer register (0x%x)\n", addr
);
752 case TIMER_CNTP_CVAL_LO
:
753 physTimer
.setCompareValue(
754 insertBits(physTimer
.compareValue(), 31, 0, value
));
757 case TIMER_CNTP_CVAL_HI
:
758 physTimer
.setCompareValue(
759 insertBits(physTimer
.compareValue(), 63, 32, value
));
762 case TIMER_CNTP_TVAL
:
763 physTimer
.setTimerValue(value
);
767 physTimer
.setControl(value
);
770 case TIMER_CNTV_CVAL_LO
:
771 virtTimer
.setCompareValue(
772 insertBits(virtTimer
.compareValue(), 31, 0, value
));
775 case TIMER_CNTV_CVAL_HI
:
776 virtTimer
.setCompareValue(
777 insertBits(virtTimer
.compareValue(), 63, 32, value
));
780 case TIMER_CNTV_TVAL
:
781 virtTimer
.setTimerValue(value
);
785 virtTimer
.setControl(value
);
789 warn("Unexpected address (0x%x:%i), ignoring write\n", addr
, size
);
792 } else if (size
== 8) {
794 case TIMER_CNTP_CVAL_LO
:
795 return physTimer
.setCompareValue(value
);
797 case TIMER_CNTV_CVAL_LO
:
798 return virtTimer
.setCompareValue(value
);
801 warn("Unexpected address (0x%x:%i), ignoring write\n", addr
, size
);
805 panic("Invalid access size: %i\n", size
);
810 GenericTimerParams::create()
812 return new GenericTimer(this);
816 GenericTimerMemParams::create()
818 return new GenericTimerMem(this);