src/dev/arm/generic_timer.hh

   1 /*
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  37
  38 #ifndef __DEV_ARM_GENERIC_TIMER_HH__
  39 #define __DEV_ARM_GENERIC_TIMER_HH__
  40
  41 #include "arch/arm/isa_device.hh"
  42 #include "arch/arm/system.hh"
  43 #include "dev/arm/base_gic.hh"
  44 #include "dev/arm/generic_timer_miscregs_types.hh"
  45 #include "sim/core.hh"
  46 #include "sim/sim_object.hh"
  47
  48 /// @file
  49 /// This module implements the global system counter and the local per-CPU
  50 /// architected timers as specified by the ARM Generic Timer extension:
  51 /// Arm ARM (ARM DDI 0487E.a)
  52 ///     D11.1.2 - The system counter
  53 ///     D11.2 - The AArch64 view of the Generic Timer
  54 ///     G6.2  - The AArch32 view of the Generic Timer
  55 ///     I2 - System Level Implementation of the Generic Timer
  56
  57 class Checkpoint;
  58 class SystemCounterParams;
  59 class GenericTimerParams;
  60 class GenericTimerFrameParams;
  61 class GenericTimerMemParams;
  62
  63 /// Abstract class for elements whose events depend on the counting speed
  64 /// of the System Counter
  65 class SystemCounterListener : public Serializable
  66 {
  67   public:
  68     /// Called from the SystemCounter when a change in counting speed occurred
  69     /// Events should be rescheduled properly inside this member function
  70     virtual void notify(void) = 0;
  71 };
  72
  73 /// Global system counter.  It is shared by the architected and memory-mapped
  74 /// timers.
  75 class SystemCounter : public SimObject
  76 {
  77   protected:
  78     /// Indicates if the counter is enabled
  79     bool _enabled;
  80     /// Counter frequency (as specified by CNTFRQ).
  81     uint32_t _freq;
  82     /// Counter value (as specified in CNTCV).
  83     uint64_t _value;
  84     /// Value increment in each counter cycle
  85     uint64_t _increment;
  86     /// Frequency modes table with all possible frequencies for the counter
  87     std::vector<uint32_t> _freqTable;
  88     /// Currently selected entry in the table, its contents should match _freq
  89     size_t _activeFreqEntry;
  90     /// Cached copy of the counter period (inverse of the frequency).
  91     Tick _period;
  92     /// Counter cycle start Tick when the counter status affecting
  93     /// its value has been updated
  94     Tick _updateTick;
  95
  96     /// Listeners to changes in counting speed
  97     std::vector<SystemCounterListener *> _listeners;
  98
  99     /// Maximum architectural number of frequency table entries
 100     static constexpr size_t MAX_FREQ_ENTRIES = 1004;
 101
 102   public:
 103     SystemCounter(SystemCounterParams *const p);
 104
 105     /// Validates a System Counter reference
 106     /// @param sys_cnt System counter reference to validate
 107     static void validateCounterRef(SystemCounter *sys_cnt);
 108
 109     /// Indicates if the counter is enabled.
 110     bool enabled() const { return _enabled; }
 111     /// Returns the counter frequency.
 112     uint32_t freq() const { return _freq; }
 113     /// Updates and returns the counter value.
 114     uint64_t value();
 115     /// Returns the value increment
 116     uint64_t increment() const { return _increment; }
 117     /// Returns a reference to the frequency modes table.
 118     std::vector<uint32_t>& freqTable() { return _freqTable; }
 119     /// Returns the currently active frequency table entry.
 120     size_t activeFreqEntry() const { return _activeFreqEntry; }
 121     /// Returns the counter period.
 122     Tick period() const { return _period; }
 123
 124     /// Enables the counter after a CNTCR.EN == 1
 125     void enable();
 126     /// Disables the counter after a CNTCR.EN == 0
 127     void disable();
 128
 129     /// Schedules a counter frequency update after a CNTCR.FCREQ == 1
 130     /// This complies with frequency transitions as per the architecture
 131     /// @param new_freq_entry Index in CNTFID of the new freq
 132     void freqUpdateSchedule(size_t new_freq_entry);
 133
 134     /// Sets the value explicitly from writes to CNTCR.CNTCV
 135     void setValue(uint64_t new_value);
 136
 137     /// Called from System Counter Listeners to register
 138     void registerListener(SystemCounterListener *listener);
 139
 140     /// Returns the tick at which a certain counter value is reached
 141     Tick whenValue(uint64_t target_val);
 142     Tick whenValue(uint64_t cur_val, uint64_t target_val) const;
 143
 144     void serialize(CheckpointOut &cp) const override;
 145     void unserialize(CheckpointIn &cp) override;
 146
 147   private:
 148     // Disable copying
 149     SystemCounter(const SystemCounter &c);
 150
 151     /// Frequency update event handling
 152     EventFunctionWrapper _freqUpdateEvent;
 153     size_t _nextFreqEntry;
 154     /// Callback for the frequency update
 155     void freqUpdateCallback();
 156
 157     /// Updates the counter value.
 158     void updateValue(void);
 159
 160     /// Updates the update tick, normalizes to the lower cycle start tick
 161     void updateTick(void);
 162
 163     /// Notifies counting speed changes to listeners
 164     void notifyListeners(void) const;
 165 };
 166
 167 /// Per-CPU architected timer.
 168 class ArchTimer : public SystemCounterListener, public Drainable
 169 {
 170   protected:
 171     /// Control register.
 172     BitUnion32(ArchTimerCtrl)
 173     Bitfield<0> enable;
 174     Bitfield<1> imask;
 175     Bitfield<2> istatus;
 176     EndBitUnion(ArchTimerCtrl)
 177
 178     /// Name of this timer.
 179     const std::string _name;
 180
 181     /// Pointer to parent class.
 182     SimObject &_parent;
 183
 184     SystemCounter &_systemCounter;
 185
 186     ArmInterruptPin * const _interrupt;
 187
 188     /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
 189     ArchTimerCtrl _control;
 190     /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
 191     uint64_t _counterLimit;
 192     /// Offset relative to the physical timer (CNTVOFF)
 193     uint64_t _offset;
 194
 195     /**
 196      * Timer settings or the offset has changed, re-evaluate
 197      * trigger condition and raise interrupt if necessary.
 198      */
 199     void updateCounter();
 200
 201     /// Called when the upcounter reaches the programmed value.
 202     void counterLimitReached();
 203     EventFunctionWrapper _counterLimitReachedEvent;
 204
 205     virtual bool scheduleEvents() { return true; }
 206
 207   public:
 208     ArchTimer(const std::string &name,
 209               SimObject &parent,
 210               SystemCounter &sysctr,
 211               ArmInterruptPin *interrupt);
 212
 213     /// Returns the timer name.
 214     std::string name() const { return _name; }
 215
 216     /// Returns the CompareValue view of the timer.
 217     uint64_t compareValue() const { return _counterLimit; }
 218     /// Sets the CompareValue view of the timer.
 219     void setCompareValue(uint64_t val);
 220
 221     /// Returns the TimerValue view of the timer.
 222     uint32_t timerValue() const { return _counterLimit - value(); }
 223     /// Sets the TimerValue view of the timer.
 224     void setTimerValue(uint32_t val);
 225
 226     /// Sets the control register.
 227     uint32_t control() const { return _control; }
 228     void setControl(uint32_t val);
 229
 230     uint64_t offset() const { return _offset; }
 231     void setOffset(uint64_t val);
 232
 233     /// Returns the value of the counter which this timer relies on.
 234     uint64_t value() const;
 235     Tick whenValue(uint64_t target_val) {
 236         return _systemCounter.whenValue(value(), target_val);
 237     }
 238
 239     void notify(void) override;
 240
 241     // Serializable
 242     void serialize(CheckpointOut &cp) const override;
 243     void unserialize(CheckpointIn &cp) override;
 244
 245     // Drainable
 246     DrainState drain() override;
 247     void drainResume() override;
 248
 249   private:
 250     // Disable copying
 251     ArchTimer(const ArchTimer &t);
 252 };
 253
 254 class ArchTimerKvm : public ArchTimer
 255 {
 256   private:
 257     ArmSystem &system;
 258
 259   public:
 260     ArchTimerKvm(const std::string &name,
 261                  ArmSystem &system,
 262                  SimObject &parent,
 263                  SystemCounter &sysctr,
 264                  ArmInterruptPin *interrupt)
 265       : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
 266
 267   protected:
 268     // For ArchTimer's in a GenericTimerISA with Kvm execution about
 269     // to begin, skip rescheduling the event.
 270     // Otherwise, we should reschedule the event (if necessary).
 271     bool scheduleEvents() override {
 272         return !system.validKvmEnvironment();
 273     }
 274 };
 275
 276 class GenericTimer : public SimObject
 277 {
 278   public:
 279     const GenericTimerParams * params() const;
 280
 281     GenericTimer(GenericTimerParams *const p);
 282
 283     void serialize(CheckpointOut &cp) const override;
 284     void unserialize(CheckpointIn &cp) override;
 285
 286   public:
 287     void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
 288     RegVal readMiscReg(int misc_reg, unsigned cpu);
 289
 290   protected:
 291     class CoreTimers : public SystemCounterListener
 292     {
 293       public:
 294         CoreTimers(GenericTimer &_parent, ArmSystem &system, unsigned cpu,
 295                    ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
 296                    ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
 297             : parent(_parent),
 298               threadContext(system.getThreadContext(cpu)),
 299               irqPhysS(_irqPhysS),
 300               irqPhysNS(_irqPhysNS),
 301               irqVirt(_irqVirt),
 302               irqHyp(_irqHyp),
 303               physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu),
 304                      system, parent, parent.systemCounter,
 305                      _irqPhysS),
 306               // This should really be phys_timerN, but we are stuck with
 307               // arch_timer for backwards compatibility.
 308               physNS(csprintf("%s.arch_timer%d", parent.name(), cpu),
 309                      system, parent, parent.systemCounter,
 310                      _irqPhysNS),
 311               virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
 312                    system, parent, parent.systemCounter,
 313                    _irqVirt),
 314               hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu),
 315                    system, parent, parent.systemCounter,
 316                    _irqHyp),
 317               physEvStream{
 318                    EventFunctionWrapper([this]{ physEventStreamCallback(); },
 319                    csprintf("%s.phys_event_gen%d", parent.name(), cpu)), 0, 0
 320               },
 321               virtEvStream{
 322                    EventFunctionWrapper([this]{ virtEventStreamCallback(); },
 323                    csprintf("%s.virt_event_gen%d", parent.name(), cpu)), 0, 0
 324               }
 325         {
 326             cntfrq = 0x01800000;
 327         }
 328
 329         /// System counter frequency as visible from this core
 330         uint32_t cntfrq;
 331
 332         /// Kernel control register
 333         CNTKCTL cntkctl;
 334
 335         /// Hypervisor control register
 336         CNTHCTL cnthctl;
 337
 338         /// Generic Timer parent reference
 339         GenericTimer &parent;
 340
 341         /// Thread (HW) context associated to this PE implementation
 342         ThreadContext *threadContext;
 343
 344         ArmInterruptPin const *irqPhysS;
 345         ArmInterruptPin const *irqPhysNS;
 346         ArmInterruptPin const *irqVirt;
 347         ArmInterruptPin const *irqHyp;
 348
 349         ArchTimerKvm physS;
 350         ArchTimerKvm physNS;
 351         ArchTimerKvm virt;
 352         ArchTimerKvm hyp;
 353
 354         // Event Stream. Events are generated based on a configurable
 355         // transitionBit over the counter value. transitionTo indicates
 356         // the transition direction (0->1 or 1->0)
 357         struct EventStream
 358         {
 359             EventFunctionWrapper event;
 360             uint8_t transitionTo;
 361             uint8_t transitionBit;
 362
 363             uint64_t
 364             eventTargetValue(uint64_t val) const
 365             {
 366                 uint64_t bit_val = bits(val, transitionBit);
 367                 uint64_t ret_val = mbits(val, 63, transitionBit);
 368                 uint64_t incr_val = 1 << transitionBit;
 369                 if (bit_val == transitionTo)
 370                     incr_val *= 2;
 371                 return ret_val + incr_val;
 372             }
 373         };
 374
 375         EventStream physEvStream;
 376         EventStream virtEvStream;
 377         void physEventStreamCallback();
 378         void virtEventStreamCallback();
 379         void eventStreamCallback() const;
 380         void schedNextEvent(EventStream &ev_stream, ArchTimer &timer);
 381
 382         void notify(void) override;
 383
 384         void serialize(CheckpointOut &cp) const override;
 385         void unserialize(CheckpointIn &cp) override;
 386
 387       private:
 388         // Disable copying
 389         CoreTimers(const CoreTimers &c);
 390     };
 391
 392     CoreTimers &getTimers(int cpu_id);
 393     void createTimers(unsigned cpus);
 394
 395     /// System counter reference.
 396     SystemCounter &systemCounter;
 397
 398     /// Per-CPU physical architected timers.
 399     std::vector<std::unique_ptr<CoreTimers>> timers;
 400
 401   protected: // Configuration
 402     /// ARM system containing this timer
 403     ArmSystem &system;
 404
 405     void handleStream(CoreTimers::EventStream *ev_stream,
 406         ArchTimer *timer, RegVal old_cnt_ctl, RegVal cnt_ctl);
 407 };
 408
 409 class GenericTimerISA : public ArmISA::BaseISADevice
 410 {
 411   public:
 412     GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
 413         : parent(_parent), cpu(_cpu) {}
 414
 415     void setMiscReg(int misc_reg, RegVal val) override;
 416     RegVal readMiscReg(int misc_reg) override;
 417
 418   protected:
 419     GenericTimer &parent;
 420     unsigned cpu;
 421 };
 422
 423 class GenericTimerFrame : public PioDevice
 424 {
 425   public:
 426     GenericTimerFrame(GenericTimerFrameParams *const p);
 427
 428     void serialize(CheckpointOut &cp) const override;
 429     void unserialize(CheckpointIn &cp) override;
 430
 431     /// Indicates if this frame implements a virtual timer
 432     bool hasVirtualTimer() const;
 433
 434     /// Returns the virtual offset for this frame if a virtual timer is
 435     /// implemented
 436     uint64_t getVirtOffset() const;
 437
 438     /// Sets the virtual offset for this frame's virtual timer after
 439     /// a write to CNTVOFF
 440     void setVirtOffset(uint64_t new_offset);
 441
 442     /// Indicates if this frame implements a second EL0 view
 443     bool hasEl0View() const;
 444
 445     /// Returns the access bits for this frame
 446     uint8_t getAccessBits() const;
 447
 448     /// Updates the access bits after a write to CNTCTLBase.CNTACR
 449     void setAccessBits(uint8_t data);
 450
 451     /// Indicates if non-secure accesses are allowed to this frame
 452     bool hasNonSecureAccess() const;
 453
 454     /// Allows non-secure accesses after an enabling write to
 455     /// CNTCTLBase.CNTNSAR
 456     void setNonSecureAccess();
 457
 458     /// Indicates if CNTVOFF is readable for this frame
 459     bool hasReadableVoff() const;
 460
 461   protected:
 462     AddrRangeList getAddrRanges() const override;
 463     Tick read(PacketPtr pkt) override;
 464     Tick write(PacketPtr pkt) override;
 465
 466   private:
 467     /// CNTBase/CNTEL0Base (Memory-mapped timer frame)
 468     uint64_t timerRead(Addr addr, size_t size, bool is_sec, bool to_el0) const;
 469     void timerWrite(Addr addr, size_t size, uint64_t data, bool is_sec,
 470                     bool to_el0);
 471     const AddrRange timerRange;
 472     AddrRange timerEl0Range;
 473
 474     static const Addr TIMER_CNTPCT_LO          = 0x00;
 475     static const Addr TIMER_CNTPCT_HI          = 0x04;
 476     static const Addr TIMER_CNTVCT_LO          = 0x08;
 477     static const Addr TIMER_CNTVCT_HI          = 0x0c;
 478     static const Addr TIMER_CNTFRQ             = 0x10;
 479     static const Addr TIMER_CNTEL0ACR          = 0x14;
 480     static const Addr TIMER_CNTVOFF_LO         = 0x18;
 481     static const Addr TIMER_CNTVOFF_HI         = 0x1c;
 482     static const Addr TIMER_CNTP_CVAL_LO       = 0x20;
 483     static const Addr TIMER_CNTP_CVAL_HI       = 0x24;
 484     static const Addr TIMER_CNTP_TVAL          = 0x28;
 485     static const Addr TIMER_CNTP_CTL           = 0x2c;
 486     static const Addr TIMER_CNTV_CVAL_LO       = 0x30;
 487     static const Addr TIMER_CNTV_CVAL_HI       = 0x34;
 488     static const Addr TIMER_CNTV_TVAL          = 0x38;
 489     static const Addr TIMER_CNTV_CTL           = 0x3c;
 490
 491     /// All MMIO ranges GenericTimerFrame responds to
 492     AddrRangeList addrRanges;
 493
 494     /// System counter reference.
 495     SystemCounter &systemCounter;
 496
 497     /// Physical and virtual timers
 498     ArchTimer physTimer;
 499     ArchTimer virtTimer;
 500
 501     /// Reports access properties of the CNTBase register frame elements
 502     BitUnion8(AccessBits)
 503         Bitfield<5> rwpt;
 504         Bitfield<4> rwvt;
 505         Bitfield<3> rvoff;
 506         Bitfield<2> rfrq;
 507         Bitfield<1> rvct;
 508         Bitfield<0> rpct;
 509     EndBitUnion(AccessBits)
 510     AccessBits accessBits;
 511
 512     // Reports access properties of the CNTEL0Base register frame elements
 513     BitUnion16(AccessBitsEl0)
 514         Bitfield<9> pten;
 515         Bitfield<8> vten;
 516         Bitfield<1> vcten;
 517         Bitfield<0> pcten;
 518     EndBitUnion(AccessBitsEl0)
 519     AccessBitsEl0 accessBitsEl0;
 520
 521     /// Reports whether non-secure accesses are allowed to this frame
 522     bool nonSecureAccess;
 523
 524     ArmSystem &system;
 525 };
 526
 527 class GenericTimerMem : public PioDevice
 528 {
 529   public:
 530     GenericTimerMem(GenericTimerMemParams *const p);
 531
 532     /// Validates a Generic Timer register frame address range
 533     /// @param base_addr Range of the register frame
 534     static void validateFrameRange(const AddrRange &range);
 535
 536     /// Validates an MMIO access permissions
 537     /// @param sys System reference where the acces is being made
 538     /// @param is_sec If the access is to secure memory
 539     static bool validateAccessPerm(ArmSystem &sys, bool is_sec);
 540
 541   protected:
 542     AddrRangeList getAddrRanges() const override;
 543     Tick read(PacketPtr pkt) override;
 544     Tick write(PacketPtr pkt) override;
 545
 546   private:
 547     /// CNTControlBase (System counter control frame)
 548     uint64_t counterCtrlRead(Addr addr, size_t size, bool is_sec) const;
 549     void counterCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec);
 550     const AddrRange counterCtrlRange;
 551
 552     BitUnion32(CNTCR)
 553         Bitfield<17,8> fcreq;
 554         Bitfield<2> scen;
 555         Bitfield<1> hdbg;
 556         Bitfield<0> en;
 557     EndBitUnion(CNTCR)
 558
 559     BitUnion32(CNTSR)
 560         Bitfield<31,8> fcack;
 561     EndBitUnion(CNTSR)
 562
 563     static const Addr COUNTER_CTRL_CNTCR       = 0x00;
 564     static const Addr COUNTER_CTRL_CNTSR       = 0x04;
 565     static const Addr COUNTER_CTRL_CNTCV_LO    = 0x08;
 566     static const Addr COUNTER_CTRL_CNTCV_HI    = 0x0c;
 567     static const Addr COUNTER_CTRL_CNTSCR      = 0x10;
 568     static const Addr COUNTER_CTRL_CNTID       = 0x1c;
 569     static const Addr COUNTER_CTRL_CNTFID      = 0x20;
 570
 571     /// CNTReadBase (System counter status frame)
 572     uint64_t counterStatusRead(Addr addr, size_t size) const;
 573     void counterStatusWrite(Addr addr, size_t size, uint64_t data);
 574     const AddrRange counterStatusRange;
 575
 576     static const Addr COUNTER_STATUS_CNTCV_LO  = 0x00;
 577     static const Addr COUNTER_STATUS_CNTCV_HI  = 0x04;
 578
 579     /// CNTCTLBase (Memory-mapped timer global control frame)
 580     uint64_t timerCtrlRead(Addr addr, size_t size, bool is_sec) const;
 581     void timerCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec);
 582     const AddrRange timerCtrlRange;
 583
 584     /// ID register for reporting features of implemented timer frames
 585     uint32_t cnttidr;
 586
 587     static const Addr TIMER_CTRL_CNTFRQ        = 0x00;
 588     static const Addr TIMER_CTRL_CNTNSAR       = 0x04;
 589     static const Addr TIMER_CTRL_CNTTIDR       = 0x08;
 590     static const Addr TIMER_CTRL_CNTACR        = 0x40;
 591     static const Addr TIMER_CTRL_CNTVOFF_LO    = 0x80;
 592     static const Addr TIMER_CTRL_CNTVOFF_HI    = 0x84;
 593
 594     /// All MMIO ranges GenericTimerMem responds to
 595     const AddrRangeList addrRanges;
 596
 597     /// System counter reference.
 598     SystemCounter &systemCounter;
 599
 600     /// Maximum architectural number of memory-mapped timer frames
 601     static constexpr size_t MAX_TIMER_FRAMES = 8;
 602
 603     /// Timer frame references
 604     std::vector<GenericTimerFrame *> frames;
 605
 606     ArmSystem &system;
 607 };
 608
 609 #endif // __DEV_ARM_GENERIC_TIMER_HH__