src/dev/arm/generic_timer_miscregs_types.hh

   1 /*
   2  * Copyright (c) 2020 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
  39 #define __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
  40
  41 #include "base/bitunion.hh"
  42
  43 namespace ArmISA
  44 {
  45     BitUnion64(CNTKCTL)
  46         // IF Armv8.6-ECV
  47         Bitfield<17> evntis;
  48         // ENDIF Armv8.6-ECV
  49         Bitfield<9> el0pten;
  50         Bitfield<8> el0vten;
  51         Bitfield<7,4> evnti;
  52         Bitfield<3> evntdir;
  53         Bitfield<2> evnten;
  54         Bitfield<1> el0vcten;
  55         Bitfield<0> el0pcten;
  56     EndBitUnion(CNTKCTL)
  57
  58     BitUnion64(CNTHCTL)
  59         // IF Armv8.6-ECV
  60         Bitfield<17> evntis;
  61         Bitfield<16> el1nvvct;
  62         Bitfield<15> el1nvpct;
  63         Bitfield<14> el1tvct;
  64         Bitfield<13> el1tvt;
  65         Bitfield<12> ecv;
  66         // ENDIF Armv8.6-ECV
  67         Bitfield<7,4> evnti;
  68         Bitfield<3> evntdir;
  69         Bitfield<2> evnten;
  70         Bitfield<1> el1pcen;
  71         Bitfield<0> el1pcten;
  72     EndBitUnion(CNTHCTL)
  73     // IF Armv8.1-VHE && HCR_EL2.E2H == 1
  74     BitUnion64(CNTHCTL_E2H)
  75         // IF Armv8.6-ECV
  76         Bitfield<17> evntis;
  77         Bitfield<16> el1nvvct;
  78         Bitfield<15> el1nvpct;
  79         Bitfield<14> el1tvct;
  80         Bitfield<13> el1tvt;
  81         Bitfield<12> ecv;
  82         // ENDIF Armv8.6-ECV
  83         Bitfield<11> el1pten;
  84         Bitfield<10> el1pcten;
  85         Bitfield<9> el0pten;
  86         Bitfield<8> el0vten;
  87         Bitfield<7,4> evnti;
  88         Bitfield<3> evntdir;
  89         Bitfield<2> evnten;
  90         Bitfield<1> el0vcten;
  91         Bitfield<0> el0pcten;
  92     EndBitUnion(CNTHCTL_E2H)
  93     // ENDIF Armv8.1-VHE && HCR_EL2.E2H == 1
  94 }
  95
  96 #endif // __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__