src/dev/arm/gic_pl390.hh

   1 /*
   2  * Copyright (c) 2010, 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43
  44 /** @file
  45  * Implementiation of a PL390 GIC
  46  */
  47
  48 #ifndef __DEV_ARM_GIC_PL390_H__
  49 #define __DEV_ARM_GIC_PL390_H__
  50
  51 #include "base/bitunion.hh"
  52 #include "cpu/intr_control.hh"
  53 #include "dev/arm/base_gic.hh"
  54 #include "dev/io_device.hh"
  55 #include "dev/platform.hh"
  56 #include "params/Pl390.hh"
  57
  58 /** @todo this code only assumes one processor for now. Low word
  59  * of intEnabled and pendingInt need to be replicated per CPU.
  60  * bottom 31 interrupts (7 words) need to be replicated for
  61  * for interrupt priority register, processor target registers
  62  * interrupt config registers  */
  63
  64 class Pl390 : public BaseGic
  65 {
  66   protected:
  67     // distributor memory addresses
  68     static const int ICDDCR     = 0x000; // control register
  69     static const int ICDICTR    = 0x004; // controller type
  70     static const int ICDIIDR    = 0x008; // implementer id
  71     static const int ICDISER_ST = 0x100; // interrupt set enable
  72     static const int ICDISER_ED = 0x17c;
  73     static const int ICDICER_ST = 0x180; // interrupt clear enable
  74     static const int ICDICER_ED = 0x1fc;
  75     static const int ICDISPR_ST = 0x200; // set pending interrupt
  76     static const int ICDISPR_ED = 0x27c;
  77     static const int ICDICPR_ST = 0x280; // clear pending interrupt
  78     static const int ICDICPR_ED = 0x2fc;
  79     static const int ICDABR_ST  = 0x300; // active bit registers
  80     static const int ICDABR_ED  = 0x37c;
  81     static const int ICDIPR_ST  = 0x400; // interrupt priority registers
  82     static const int ICDIPR_ED  = 0x7f8;
  83     static const int ICDIPTR_ST = 0x800; // processor target registers
  84     static const int ICDIPTR_ED = 0xbf8;
  85     static const int ICDICFR_ST = 0xc00; // interrupt config registers
  86     static const int ICDICFR_ED = 0xcfc;
  87     static const int ICDSGIR    = 0xf00; // software generated interrupt
  88     static const int DIST_SIZE  = 0xfff;
  89
  90     // cpu memory addressesa
  91     static const int ICCICR  = 0x00; // CPU control register
  92     static const int ICCPMR  = 0x04; // Interrupt priority mask
  93     static const int ICCBPR  = 0x08; // binary point register
  94     static const int ICCIAR  = 0x0C; // interrupt ack register
  95     static const int ICCEOIR = 0x10; // end of interrupt
  96     static const int ICCRPR  = 0x14; // runing priority
  97     static const int ICCHPIR = 0x18; // highest pending interrupt
  98     static const int ICCABPR = 0x1c; // aliased binary point
  99     static const int ICCIIDR = 0xfc; // cpu interface id register
 100     static const int CPU_SIZE  = 0xff;
 101
 102     static const int SGI_MAX = 16;  // Number of Software Gen Interrupts
 103     static const int PPI_MAX = 16;  // Number of Private Peripheral Interrupts
 104
 105     /** Mask off SGI's when setting/clearing pending bits */
 106     static const int SGI_MASK = 0xFFFF0000;
 107
 108     /** Mask for bits that config N:N mode in ICDICFR's */
 109     static const int NN_CONFIG_MASK = 0x55555555;
 110
 111     static const int CPU_MAX = 8;   // Max number of supported CPU interfaces
 112     static const int SPURIOUS_INT = 1023;
 113     static const int INT_BITS_MAX = 32;
 114     static const int INT_LINES_MAX = 1020;
 115
 116     BitUnion32(SWI)
 117         Bitfield<3,0> sgi_id;
 118         Bitfield<23,16> cpu_list;
 119         Bitfield<25,24> list_type;
 120     EndBitUnion(SWI)
 121
 122     BitUnion32(IAR)
 123         Bitfield<9,0> ack_id;
 124         Bitfield<12,10> cpu_id;
 125     EndBitUnion(IAR)
 126
 127     /** Distributor address GIC listens at */
 128     Addr distAddr;
 129
 130     /** CPU address GIC listens at */
 131     /** @todo is this one per cpu? */
 132     Addr cpuAddr;
 133
 134     /** Latency for a distributor operation */
 135     Tick distPioDelay;
 136
 137     /** Latency for a cpu operation */
 138     Tick cpuPioDelay;
 139
 140     /** Latency for a interrupt to get to CPU */
 141     Tick intLatency;
 142
 143     /** Gic enabled */
 144     bool enabled;
 145
 146     /** Number of itLines enabled */
 147     uint32_t itLines;
 148
 149     uint32_t itLinesLog2;
 150
 151     /** interrupt enable bits for all possible 1020 interupts.
 152      * one bit per interrupt, 32 bit per word = 32 words */
 153     uint32_t intEnabled[INT_BITS_MAX];
 154
 155     /** interrupt pending bits for all possible 1020 interupts.
 156      * one bit per interrupt, 32 bit per word = 32 words */
 157     uint32_t pendingInt[INT_BITS_MAX];
 158
 159     /** interrupt active bits for all possible 1020 interupts.
 160      * one bit per interrupt, 32 bit per word = 32 words */
 161     uint32_t activeInt[INT_BITS_MAX];
 162
 163     /** read only running priroity register, 1 per cpu*/
 164     uint32_t iccrpr[CPU_MAX];
 165
 166     /** an 8 bit priority (lower is higher priority) for each
 167      * of the 1020 possible supported interrupts.
 168      */
 169     uint8_t intPriority[INT_LINES_MAX];
 170
 171     /** an 8 bit cpu target id for each shared peripheral interrupt
 172      * of the 1020 possible supported interrupts.
 173      */
 174     uint8_t cpuTarget[INT_LINES_MAX];
 175
 176     /** 2 bit per interrupt signaling if it's level or edge sensitive
 177      * and if it is 1:N or N:N */
 178     uint32_t intConfig[INT_BITS_MAX*2];
 179
 180     /** CPU enabled */
 181     bool cpuEnabled[CPU_MAX];
 182
 183     /** CPU priority */
 184     uint8_t cpuPriority[CPU_MAX];
 185
 186     /** Binary point registers */
 187     uint8_t cpuBpr[CPU_MAX];
 188
 189     /** highest interrupt that is interrupting CPU */
 190     uint32_t cpuHighestInt[CPU_MAX];
 191
 192     /** One bit per cpu per software interrupt that is pending for each possible
 193      * sgi source. Indexed by SGI number. Each byte in generating cpu id and
 194      * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
 195      * for CPU 2. */
 196     uint64_t cpuSgiPending[SGI_MAX];
 197     uint64_t cpuSgiActive[SGI_MAX];
 198
 199     /** One bit per private peripheral interrupt. Only upper 16 bits
 200      * will be used since PPI interrupts are numberred from 16 to 32 */
 201     uint32_t cpuPpiPending[CPU_MAX];
 202     uint32_t cpuPpiActive[CPU_MAX];
 203
 204     /** Banked interrupt prioirty registers for SGIs and PPIs */
 205     uint8_t bankedIntPriority[CPU_MAX][SGI_MAX + PPI_MAX];
 206
 207     /** IRQ Enable Used for debug */
 208     bool irqEnable;
 209
 210     /** software generated interrupt
 211      * @param data data to decode that indicates which cpus to interrupt
 212      */
 213     void softInt(int ctx_id, SWI swi);
 214
 215     /** See if some processor interrupt flags need to be enabled/disabled
 216      * @param hint which set of interrupts needs to be checked
 217      */
 218     void updateIntState(int hint);
 219
 220     /** Update the register that records priority of the highest priority
 221      *  active interrupt*/
 222     void updateRunPri();
 223
 224     /** generate a bit mask to check cpuSgi for an interrupt. */
 225     uint64_t genSwiMask(int cpu);
 226
 227     int intNumToWord(int num) const { return num >> 5; }
 228     int intNumToBit(int num) const { return num % 32; }
 229
 230     /** Post an interrupt to a CPU
 231      */
 232     void postInt(uint32_t cpu, Tick when);
 233
 234     /** Event definition to post interrupt to CPU after a delay
 235     */
 236     class PostIntEvent : public Event
 237     {
 238       private:
 239         uint32_t cpu;
 240         Platform *platform;
 241       public:
 242         PostIntEvent( uint32_t c, Platform* p)
 243             : cpu(c), platform(p)
 244         { }
 245         void process() { platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);}
 246         const char *description() const { return "Post Interrupt to CPU"; }
 247     };
 248     PostIntEvent *postIntEvent[CPU_MAX];
 249
 250   public:
 251     typedef Pl390Params Params;
 252     const Params *
 253     params() const
 254     {
 255         return dynamic_cast<const Params *>(_params);
 256     }
 257     Pl390(const Params *p);
 258
 259     /** @{ */
 260     /** Return the address ranges used by the Gic
 261      * This is the distributor address + all cpu addresses
 262      */
 263     virtual AddrRangeList getAddrRanges() const;
 264
 265     /** A PIO read to the device, immediately split up into
 266      * readDistributor() or readCpu()
 267      */
 268     virtual Tick read(PacketPtr pkt);
 269
 270     /** A PIO read to the device, immediately split up into
 271      * writeDistributor() or writeCpu()
 272      */
 273     virtual Tick write(PacketPtr pkt);
 274     /** @} */
 275
 276     /** @{ */
 277     /** Post an interrupt from a device that is connected to the Gic.
 278      * Depending on the configuration, the gic will pass this interrupt
 279      * on through to a CPU.
 280      * @param number number of interrupt to send */
 281     void sendInt(uint32_t number);
 282
 283     /** Interface call for private peripheral interrupts  */
 284     void sendPPInt(uint32_t num, uint32_t cpu);
 285
 286     /** Clear an interrupt from a device that is connected to the Gic
 287      * Depending on the configuration, the gic may de-assert it's cpu line
 288      * @param number number of interrupt to send */
 289     void clearInt(uint32_t number);
 290
 291     /** Clear a (level-sensitive) PPI */
 292     void clearPPInt(uint32_t num, uint32_t cpu);
 293     /** @} */
 294
 295     /** @{ */
 296     /* Various functions fer testing and debugging */
 297     void driveSPI(uint32_t spi);
 298     void driveLegIRQ(bool state);
 299     void driveLegFIQ(bool state);
 300     void driveIrqEn(bool state);
 301     /** @} */
 302
 303     virtual void serialize(std::ostream &os);
 304     virtual void unserialize(Checkpoint *cp, const std::string &section);
 305
 306   protected:
 307     /** Handle a read to the distributor poriton of the GIC
 308      * @param pkt packet to respond to
 309      */
 310     Tick readDistributor(PacketPtr pkt);
 311
 312     /** Handle a read to the cpu poriton of the GIC
 313      * @param pkt packet to respond to
 314      */
 315     Tick readCpu(PacketPtr pkt);
 316
 317     /** Handle a write to the distributor poriton of the GIC
 318      * @param pkt packet to respond to
 319      */
 320     Tick writeDistributor(PacketPtr pkt);
 321
 322     /** Handle a write to the cpu poriton of the GIC
 323      * @param pkt packet to respond to
 324      */
 325     Tick writeCpu(PacketPtr pkt);
 326 };
 327
 328 #endif //__DEV_ARM_GIC_H__