src/dev/arm/gic_pl390.hh

   1 /*
   2  * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43
  44 /** @file
  45  * Implementation of a PL390 GIC
  46  */
  47
  48 #ifndef __DEV_ARM_GIC_PL390_H__
  49 #define __DEV_ARM_GIC_PL390_H__
  50
  51 #include <vector>
  52
  53 #include "base/addr_range.hh"
  54 #include "base/bitunion.hh"
  55 #include "cpu/intr_control.hh"
  56 #include "dev/arm/base_gic.hh"
  57 #include "dev/io_device.hh"
  58 #include "dev/platform.hh"
  59 #include "params/Pl390.hh"
  60
  61 class Pl390 : public BaseGic, public BaseGicRegisters
  62 {
  63   protected:
  64     // distributor memory addresses
  65     enum {
  66         GICD_CTLR          = 0x000, // control register
  67         GICD_TYPER         = 0x004, // controller type
  68         GICD_IIDR          = 0x008, // implementer id
  69         GICD_SGIR          = 0xf00, // software generated interrupt
  70         GICD_PIDR0         = 0xfe0, // distributor peripheral ID0
  71         GICD_PIDR1         = 0xfe4, // distributor peripheral ID1
  72         GICD_PIDR2         = 0xfe8, // distributor peripheral ID2
  73         GICD_PIDR3         = 0xfec, // distributor peripheral ID3
  74
  75         DIST_SIZE          = 0x1000,
  76     };
  77
  78     /**
  79      * As defined in:
  80      * "ARM Generic Interrupt Controller Architecture" version 2.0
  81      * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
  82      */
  83     static constexpr uint32_t  GICD_400_PIDR_VALUE = 0x002bb490;
  84     static constexpr uint32_t  GICD_400_IIDR_VALUE = 0x200143B;
  85     static constexpr uint32_t  GICC_400_IIDR_VALUE = 0x202143B;
  86
  87     static const AddrRange GICD_IGROUPR;    // interrupt group (unimplemented)
  88     static const AddrRange GICD_ISENABLER;  // interrupt set enable
  89     static const AddrRange GICD_ICENABLER;  // interrupt clear enable
  90     static const AddrRange GICD_ISPENDR;    // set pending interrupt
  91     static const AddrRange GICD_ICPENDR;    // clear pending interrupt
  92     static const AddrRange GICD_ISACTIVER;  // active bit registers
  93     static const AddrRange GICD_ICACTIVER;  // clear bit registers
  94     static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
  95     static const AddrRange GICD_ITARGETSR;  // processor target registers
  96     static const AddrRange GICD_ICFGR;      // interrupt config registers
  97
  98     // cpu memory addresses
  99     enum {
 100         GICC_CTLR  = 0x00, // CPU control register
 101         GICC_PMR   = 0x04, // Interrupt priority mask
 102         GICC_BPR   = 0x08, // binary point register
 103         GICC_IAR   = 0x0C, // interrupt ack register
 104         GICC_EOIR  = 0x10, // end of interrupt
 105         GICC_RPR   = 0x14, // running priority
 106         GICC_HPPIR = 0x18, // highest pending interrupt
 107         GICC_ABPR  = 0x1c, // aliased binary point
 108         GICC_APR0  = 0xd0, // active priority register 0
 109         GICC_APR1  = 0xd4, // active priority register 1
 110         GICC_APR2  = 0xd8, // active priority register 2
 111         GICC_APR3  = 0xdc, // active priority register 3
 112         GICC_IIDR  = 0xfc, // cpu interface id register
 113     };
 114
 115     static const int SGI_MAX = 16;  // Number of Software Gen Interrupts
 116     static const int PPI_MAX = 16;  // Number of Private Peripheral Interrupts
 117
 118     /** Mask off SGI's when setting/clearing pending bits */
 119     static const int SGI_MASK = 0xFFFF0000;
 120
 121     /** Mask for bits that config N:N mode in GICD_ICFGR's */
 122     static const int NN_CONFIG_MASK = 0x55555555;
 123
 124     static const int CPU_MAX = 256;   // Max number of supported CPU interfaces
 125     static const int SPURIOUS_INT = 1023;
 126     static const int INT_BITS_MAX = 32;
 127     static const int INT_LINES_MAX = 1020;
 128     static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
 129
 130     /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
 131         chosen for consistency with Linux's in-kernel KVM GIC model */
 132     static const int GICC_BPR_MINIMUM = 2;
 133
 134     BitUnion32(SWI)
 135         Bitfield<3,0> sgi_id;
 136         Bitfield<23,16> cpu_list;
 137         Bitfield<25,24> list_type;
 138     EndBitUnion(SWI)
 139
 140     BitUnion32(IAR)
 141         Bitfield<9,0> ack_id;
 142         Bitfield<12,10> cpu_id;
 143     EndBitUnion(IAR)
 144
 145   protected: /* Params */
 146     /** Address range for the distributor interface */
 147     const AddrRange distRange;
 148
 149     /** Address range for the CPU interfaces */
 150     const AddrRange cpuRange;
 151
 152     /** All address ranges used by this GIC */
 153     const AddrRangeList addrRanges;
 154
 155     /** Latency for a distributor operation */
 156     const Tick distPioDelay;
 157
 158     /** Latency for a cpu operation */
 159     const Tick cpuPioDelay;
 160
 161     /** Latency for a interrupt to get to CPU */
 162     const Tick intLatency;
 163
 164   protected:
 165     /** Gic enabled */
 166     bool enabled;
 167
 168     /** Are gem5 extensions available? */
 169     const bool haveGem5Extensions;
 170
 171     /** gem5 many-core extension enabled by driver */
 172     bool gem5ExtensionsEnabled;
 173
 174     /** Number of itLines enabled */
 175     uint32_t itLines;
 176
 177     /** Registers "banked for each connected processor" per ARM IHI0048B */
 178     struct BankedRegs : public Serializable {
 179         /** GICD_I{S,C}ENABLER0
 180          * interrupt enable bits for first 32 interrupts, 1b per interrupt */
 181         uint32_t intEnabled;
 182
 183         /** GICD_I{S,C}PENDR0
 184          * interrupt pending bits for first 32 interrupts, 1b per interrupt */
 185         uint32_t pendingInt;
 186
 187         /** GICD_I{S,C}ACTIVER0
 188          * interrupt active bits for first 32 interrupts, 1b per interrupt */
 189         uint32_t activeInt;
 190
 191         /** GICD_IPRIORITYR{0..7}
 192          * interrupt priority for SGIs and PPIs */
 193         uint8_t intPriority[SGI_MAX + PPI_MAX];
 194
 195         void serialize(CheckpointOut &cp) const override;
 196         void unserialize(CheckpointIn &cp) override;
 197
 198         BankedRegs() :
 199             intEnabled(0), pendingInt(0), activeInt(0), intPriority {0}
 200           {}
 201     };
 202     std::vector<BankedRegs*> bankedRegs;
 203
 204     BankedRegs& getBankedRegs(ContextID);
 205
 206     /** GICD_I{S,C}ENABLER{1..31}
 207      * interrupt enable bits for global interrupts
 208      * 1b per interrupt, 32 bits per word, 31 words */
 209     uint32_t intEnabled[INT_BITS_MAX-1];
 210
 211     uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
 212         if (ix == 0) {
 213             return getBankedRegs(ctx).intEnabled;
 214         } else {
 215             return intEnabled[ix - 1];
 216         }
 217     }
 218
 219     /** GICD_I{S,C}PENDR{1..31}
 220      * interrupt pending bits for global interrupts
 221      * 1b per interrupt, 32 bits per word, 31 words */
 222     uint32_t pendingInt[INT_BITS_MAX-1];
 223
 224     uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
 225         assert(ix < INT_BITS_MAX);
 226         if (ix == 0) {
 227             return getBankedRegs(ctx).pendingInt;
 228         } else {
 229             return pendingInt[ix - 1];
 230         }
 231     }
 232
 233     /** GICD_I{S,C}ACTIVER{1..31}
 234      * interrupt active bits for global interrupts
 235      * 1b per interrupt, 32 bits per word, 31 words */
 236     uint32_t activeInt[INT_BITS_MAX-1];
 237
 238     uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
 239         assert(ix < INT_BITS_MAX);
 240         if (ix == 0) {
 241             return getBankedRegs(ctx).activeInt;
 242         } else {
 243             return activeInt[ix - 1];
 244         }
 245     }
 246
 247     /** read only running priority register, 1 per cpu*/
 248     uint32_t iccrpr[CPU_MAX];
 249
 250     /** GICD_IPRIORITYR{8..255}
 251      * an 8 bit priority (lower is higher priority) for each
 252      * of the global (not replicated per CPU) interrupts.
 253      */
 254     uint8_t intPriority[GLOBAL_INT_LINES];
 255
 256     uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
 257         assert(ix < INT_LINES_MAX);
 258         if (ix < SGI_MAX + PPI_MAX) {
 259             return getBankedRegs(ctx).intPriority[ix];
 260         } else {
 261             return intPriority[ix - (SGI_MAX + PPI_MAX)];
 262         }
 263     }
 264
 265     /** GICD_ITARGETSR{8..255}
 266      * an 8 bit cpu target id for each global interrupt.
 267      */
 268     uint8_t cpuTarget[GLOBAL_INT_LINES];
 269
 270     uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
 271         assert(ctx < sys->numRunningContexts());
 272         assert(ix < INT_LINES_MAX);
 273         if (ix < SGI_MAX + PPI_MAX) {
 274             // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
 275             // field returns a value that corresponds only to the processor
 276             // reading the register."
 277             uint32_t ctx_mask;
 278             if (gem5ExtensionsEnabled) {
 279                 ctx_mask = ctx;
 280             } else {
 281             // convert the CPU id number into a bit mask
 282                 ctx_mask = power(2, ctx);
 283             }
 284             return ctx_mask;
 285         } else {
 286             return cpuTarget[ix - 32];
 287         }
 288     }
 289
 290     /** 2 bit per interrupt signaling if it's level or edge sensitive
 291      * and if it is 1:N or N:N */
 292     uint32_t intConfig[INT_BITS_MAX*2];
 293
 294     /** CPU enabled */
 295     bool cpuEnabled[CPU_MAX];
 296
 297     /** CPU priority */
 298     uint8_t cpuPriority[CPU_MAX];
 299     uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
 300
 301     /** Binary point registers */
 302     uint8_t cpuBpr[CPU_MAX];
 303
 304     /** highest interrupt that is interrupting CPU */
 305     uint32_t cpuHighestInt[CPU_MAX];
 306
 307     /** One bit per cpu per software interrupt that is pending for each possible
 308      * sgi source. Indexed by SGI number. Each byte in generating cpu id and
 309      * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
 310      * for CPU 2. */
 311     uint64_t cpuSgiPending[SGI_MAX];
 312     uint64_t cpuSgiActive[SGI_MAX];
 313
 314     /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
 315      * 16 SGI pending bits for each of the (large number of) CPUs.
 316      */
 317     uint32_t cpuSgiPendingExt[CPU_MAX];
 318     uint32_t cpuSgiActiveExt[CPU_MAX];
 319
 320     /** One bit per private peripheral interrupt. Only upper 16 bits
 321      * will be used since PPI interrupts are numberred from 16 to 32 */
 322     uint32_t cpuPpiPending[CPU_MAX];
 323     uint32_t cpuPpiActive[CPU_MAX];
 324
 325     /** software generated interrupt
 326      * @param data data to decode that indicates which cpus to interrupt
 327      */
 328     void softInt(ContextID ctx, SWI swi);
 329
 330     /** See if some processor interrupt flags need to be enabled/disabled
 331      * @param hint which set of interrupts needs to be checked
 332      */
 333     virtual void updateIntState(int hint);
 334
 335     /** Update the register that records priority of the highest priority
 336      *  active interrupt*/
 337     void updateRunPri();
 338
 339     /** generate a bit mask to check cpuSgi for an interrupt. */
 340     uint64_t genSwiMask(int cpu);
 341
 342     int intNumToWord(int num) const { return num >> 5; }
 343     int intNumToBit(int num) const { return num % 32; }
 344
 345     /**
 346      * Post an interrupt to a CPU with a delay
 347      */
 348     void postInt(uint32_t cpu, Tick when);
 349
 350     /**
 351      * Deliver a delayed interrupt to the target CPU
 352      */
 353     void postDelayedInt(uint32_t cpu);
 354
 355     EventFunctionWrapper *postIntEvent[CPU_MAX];
 356     int pendingDelayedInterrupts;
 357
 358   public:
 359     typedef Pl390Params Params;
 360     const Params *
 361     params() const
 362     {
 363         return dynamic_cast<const Params *>(_params);
 364     }
 365     Pl390(const Params *p);
 366     ~Pl390();
 367
 368     DrainState drain() override;
 369     void drainResume() override;
 370
 371     void serialize(CheckpointOut &cp) const override;
 372     void unserialize(CheckpointIn &cp) override;
 373
 374   public: /* PioDevice */
 375     AddrRangeList getAddrRanges() const override { return addrRanges; }
 376
 377     /** A PIO read to the device, immediately split up into
 378      * readDistributor() or readCpu()
 379      */
 380     Tick read(PacketPtr pkt) override;
 381
 382     /** A PIO read to the device, immediately split up into
 383      * writeDistributor() or writeCpu()
 384      */
 385     Tick write(PacketPtr pkt) override;
 386
 387   public: /* BaseGic */
 388     void sendInt(uint32_t number) override;
 389     void clearInt(uint32_t number) override;
 390
 391     void sendPPInt(uint32_t num, uint32_t cpu) override;
 392     void clearPPInt(uint32_t num, uint32_t cpu) override;
 393
 394   protected:
 395     /** Handle a read to the distributor portion of the GIC
 396      * @param pkt packet to respond to
 397      */
 398     Tick readDistributor(PacketPtr pkt);
 399     uint32_t readDistributor(ContextID ctx, Addr daddr,
 400                              size_t resp_sz);
 401     uint32_t readDistributor(ContextID ctx, Addr daddr) override {
 402         return readDistributor(ctx, daddr, 4);
 403     }
 404
 405     /** Handle a read to the cpu portion of the GIC
 406      * @param pkt packet to respond to
 407      */
 408     Tick readCpu(PacketPtr pkt);
 409     uint32_t readCpu(ContextID ctx, Addr daddr) override;
 410
 411     /** Handle a write to the distributor portion of the GIC
 412      * @param pkt packet to respond to
 413      */
 414     Tick writeDistributor(PacketPtr pkt);
 415     void writeDistributor(ContextID ctx, Addr daddr,
 416                           uint32_t data, size_t data_sz);
 417     void writeDistributor(ContextID ctx, Addr daddr,
 418                                   uint32_t data) override {
 419         return writeDistributor(ctx, daddr, data, 4);
 420     }
 421
 422     /** Handle a write to the cpu portion of the GIC
 423      * @param pkt packet to respond to
 424      */
 425     Tick writeCpu(PacketPtr pkt);
 426     void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
 427 };
 428
 429 #endif //__DEV_ARM_GIC_H__