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45 * Implementiation of a PL390 GIC
48 #ifndef __DEV_ARM_GIC_PL390_H__
49 #define __DEV_ARM_GIC_PL390_H__
51 #include "base/bitunion.hh"
52 #include "cpu/intr_control.hh"
53 #include "dev/arm/base_gic.hh"
54 #include "dev/io_device.hh"
55 #include "dev/platform.hh"
56 #include "params/Pl390.hh"
58 /** @todo this code only assumes one processor for now. Low word
59 * of intEnabled and pendingInt need to be replicated per CPU.
60 * bottom 31 interrupts (7 words) need to be replicated for
61 * for interrupt priority register, processor target registers
62 * interrupt config registers */
64 class Pl390 : public BaseGic
67 // distributor memory addresses
68 static const int ICDDCR = 0x000; // control register
69 static const int ICDICTR = 0x004; // controller type
70 static const int ICDIIDR = 0x008; // implementer id
71 static const int ICDISER_ST = 0x100; // interrupt set enable
72 static const int ICDISER_ED = 0x17c;
73 static const int ICDICER_ST = 0x180; // interrupt clear enable
74 static const int ICDICER_ED = 0x1fc;
75 static const int ICDISPR_ST = 0x200; // set pending interrupt
76 static const int ICDISPR_ED = 0x27c;
77 static const int ICDICPR_ST = 0x280; // clear pending interrupt
78 static const int ICDICPR_ED = 0x2fc;
79 static const int ICDABR_ST = 0x300; // active bit registers
80 static const int ICDABR_ED = 0x37c;
81 static const int ICDIPR_ST = 0x400; // interrupt priority registers
82 static const int ICDIPR_ED = 0x7f8;
83 static const int ICDIPTR_ST = 0x800; // processor target registers
84 static const int ICDIPTR_ED = 0xbf8;
85 static const int ICDICFR_ST = 0xc00; // interrupt config registers
86 static const int ICDICFR_ED = 0xcfc;
87 static const int ICDSGIR = 0xf00; // software generated interrupt
88 static const int DIST_SIZE = 0xfff;
90 // cpu memory addressesa
91 static const int ICCICR = 0x00; // CPU control register
92 static const int ICCPMR = 0x04; // Interrupt priority mask
93 static const int ICCBPR = 0x08; // binary point register
94 static const int ICCIAR = 0x0C; // interrupt ack register
95 static const int ICCEOIR = 0x10; // end of interrupt
96 static const int ICCRPR = 0x14; // runing priority
97 static const int ICCHPIR = 0x18; // highest pending interrupt
98 static const int ICCABPR = 0x1c; // aliased binary point
99 static const int ICCIIDR = 0xfc; // cpu interface id register
100 static const int CPU_SIZE = 0xff;
102 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
103 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
105 /** Mask off SGI's when setting/clearing pending bits */
106 static const int SGI_MASK = 0xFFFF0000;
108 /** Mask for bits that config N:N mode in ICDICFR's */
109 static const int NN_CONFIG_MASK = 0x55555555;
111 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
112 static const int SPURIOUS_INT = 1023;
113 static const int INT_BITS_MAX = 32;
114 static const int INT_LINES_MAX = 1020;
117 Bitfield<3,0> sgi_id;
118 Bitfield<23,16> cpu_list;
119 Bitfield<25,24> list_type;
123 Bitfield<9,0> ack_id;
124 Bitfield<12,10> cpu_id;
127 /** Distributor address GIC listens at */
130 /** CPU address GIC listens at */
131 /** @todo is this one per cpu? */
134 /** Latency for a distributor operation */
137 /** Latency for a cpu operation */
140 /** Latency for a interrupt to get to CPU */
146 /** gem5 many-core extension enabled by driver */
147 bool gem5ExtensionsEnabled;
149 /** Number of itLines enabled */
152 uint32_t itLinesLog2;
154 /** interrupt enable bits for all possible 1020 interupts.
155 * one bit per interrupt, 32 bit per word = 32 words */
156 uint32_t intEnabled[INT_BITS_MAX];
158 /** interrupt pending bits for all possible 1020 interupts.
159 * one bit per interrupt, 32 bit per word = 32 words */
160 uint32_t pendingInt[INT_BITS_MAX];
162 /** interrupt active bits for all possible 1020 interupts.
163 * one bit per interrupt, 32 bit per word = 32 words */
164 uint32_t activeInt[INT_BITS_MAX];
166 /** read only running priroity register, 1 per cpu*/
167 uint32_t iccrpr[CPU_MAX];
169 /** an 8 bit priority (lower is higher priority) for each
170 * of the 1020 possible supported interrupts.
172 uint8_t intPriority[INT_LINES_MAX];
174 /** an 8 bit cpu target id for each shared peripheral interrupt
175 * of the 1020 possible supported interrupts.
177 uint8_t cpuTarget[INT_LINES_MAX];
179 /** 2 bit per interrupt signaling if it's level or edge sensitive
180 * and if it is 1:N or N:N */
181 uint32_t intConfig[INT_BITS_MAX*2];
184 bool cpuEnabled[CPU_MAX];
187 uint8_t cpuPriority[CPU_MAX];
189 /** Binary point registers */
190 uint8_t cpuBpr[CPU_MAX];
192 /** highest interrupt that is interrupting CPU */
193 uint32_t cpuHighestInt[CPU_MAX];
195 /** One bit per cpu per software interrupt that is pending for each possible
196 * sgi source. Indexed by SGI number. Each byte in generating cpu id and
197 * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
199 uint64_t cpuSgiPending[SGI_MAX];
200 uint64_t cpuSgiActive[SGI_MAX];
202 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
203 * 16 SGI pending bits for each of the (large number of) CPUs.
205 uint32_t cpuSgiPendingExt[CPU_MAX];
206 uint32_t cpuSgiActiveExt[CPU_MAX];
208 /** One bit per private peripheral interrupt. Only upper 16 bits
209 * will be used since PPI interrupts are numberred from 16 to 32 */
210 uint32_t cpuPpiPending[CPU_MAX];
211 uint32_t cpuPpiActive[CPU_MAX];
213 /** Banked interrupt prioirty registers for SGIs and PPIs */
214 uint8_t bankedIntPriority[CPU_MAX][SGI_MAX + PPI_MAX];
216 /** IRQ Enable Used for debug */
219 /** software generated interrupt
220 * @param data data to decode that indicates which cpus to interrupt
222 void softInt(ContextID ctx_id, SWI swi);
224 /** See if some processor interrupt flags need to be enabled/disabled
225 * @param hint which set of interrupts needs to be checked
227 void updateIntState(int hint);
229 /** Update the register that records priority of the highest priority
233 /** generate a bit mask to check cpuSgi for an interrupt. */
234 uint64_t genSwiMask(int cpu);
236 int intNumToWord(int num) const { return num >> 5; }
237 int intNumToBit(int num) const { return num % 32; }
239 /** Post an interrupt to a CPU
241 void postInt(uint32_t cpu, Tick when);
243 /** Event definition to post interrupt to CPU after a delay
245 class PostIntEvent : public Event
251 PostIntEvent( uint32_t c, Platform* p)
252 : cpu(c), platform(p)
254 void process() { platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);}
255 const char *description() const { return "Post Interrupt to CPU"; }
257 PostIntEvent *postIntEvent[CPU_MAX];
260 typedef Pl390Params Params;
264 return dynamic_cast<const Params *>(_params);
266 Pl390(const Params *p);
269 /** Return the address ranges used by the Gic
270 * This is the distributor address + all cpu addresses
272 AddrRangeList getAddrRanges() const override;
274 /** A PIO read to the device, immediately split up into
275 * readDistributor() or readCpu()
277 Tick read(PacketPtr pkt) override;
279 /** A PIO read to the device, immediately split up into
280 * writeDistributor() or writeCpu()
282 Tick write(PacketPtr pkt) override;
286 /** Post an interrupt from a device that is connected to the Gic.
287 * Depending on the configuration, the gic will pass this interrupt
288 * on through to a CPU.
289 * @param number number of interrupt to send */
290 void sendInt(uint32_t number) override;
292 /** Interface call for private peripheral interrupts */
293 void sendPPInt(uint32_t num, uint32_t cpu) override;
295 /** Clear an interrupt from a device that is connected to the Gic
296 * Depending on the configuration, the gic may de-assert it's cpu line
297 * @param number number of interrupt to send */
298 void clearInt(uint32_t number) override;
300 /** Clear a (level-sensitive) PPI */
301 void clearPPInt(uint32_t num, uint32_t cpu) override;
305 /* Various functions fer testing and debugging */
306 void driveSPI(uint32_t spi);
307 void driveLegIRQ(bool state);
308 void driveLegFIQ(bool state);
309 void driveIrqEn(bool state);
312 void serialize(CheckpointOut &cp) const override;
313 void unserialize(CheckpointIn &cp) override;
316 /** Handle a read to the distributor poriton of the GIC
317 * @param pkt packet to respond to
319 Tick readDistributor(PacketPtr pkt);
321 /** Handle a read to the cpu poriton of the GIC
322 * @param pkt packet to respond to
324 Tick readCpu(PacketPtr pkt);
326 /** Handle a write to the distributor poriton of the GIC
327 * @param pkt packet to respond to
329 Tick writeDistributor(PacketPtr pkt);
331 /** Handle a write to the cpu poriton of the GIC
332 * @param pkt packet to respond to
334 Tick writeCpu(PacketPtr pkt);
337 #endif //__DEV_ARM_GIC_H__