src/dev/arm/gic_pl390.hh

   1 /*
   2  * Copyright (c) 2010, 2013, 2015-2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43
  44 /** @file
  45  * Implementation of a PL390 GIC
  46  */
  47
  48 #ifndef __DEV_ARM_GIC_PL390_H__
  49 #define __DEV_ARM_GIC_PL390_H__
  50
  51 #include <vector>
  52
  53 #include "base/addr_range.hh"
  54 #include "base/bitunion.hh"
  55 #include "cpu/intr_control.hh"
  56 #include "dev/arm/base_gic.hh"
  57 #include "dev/io_device.hh"
  58 #include "dev/platform.hh"
  59 #include "params/Pl390.hh"
  60
  61 class Pl390 : public BaseGic, public BaseGicRegisters
  62 {
  63   protected:
  64     // distributor memory addresses
  65     enum {
  66         GICD_CTLR          = 0x000, // control register
  67         GICD_TYPER         = 0x004, // controller type
  68         GICD_IIDR          = 0x008, // implementer id
  69         GICD_SGIR          = 0xf00, // software generated interrupt
  70         GICD_PIDR0         = 0xfe0, // distributor peripheral ID0
  71         GICD_PIDR1         = 0xfe4, // distributor peripheral ID1
  72         GICD_PIDR2         = 0xfe8, // distributor peripheral ID2
  73         GICD_PIDR3         = 0xfec, // distributor peripheral ID3
  74
  75         DIST_SIZE          = 0xfff
  76     };
  77
  78     /**
  79      * As defined in:
  80      * "ARM Generic Interrupt Controller Architecture" version 2.0
  81      * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
  82      */
  83     static constexpr uint32_t  GICD_400_PIDR_VALUE = 0x002bb490;
  84     static constexpr uint32_t  GICD_400_IIDR_VALUE = 0x200143B;
  85     static constexpr uint32_t  GICC_400_IIDR_VALUE = 0x202143B;
  86
  87     static const AddrRange GICD_IGROUPR;    // interrupt group (unimplemented)
  88     static const AddrRange GICD_ISENABLER;  // interrupt set enable
  89     static const AddrRange GICD_ICENABLER;  // interrupt clear enable
  90     static const AddrRange GICD_ISPENDR;    // set pending interrupt
  91     static const AddrRange GICD_ICPENDR;    // clear pending interrupt
  92     static const AddrRange GICD_ISACTIVER;  // active bit registers
  93     static const AddrRange GICD_ICACTIVER;  // clear bit registers
  94     static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
  95     static const AddrRange GICD_ITARGETSR;  // processor target registers
  96     static const AddrRange GICD_ICFGR;      // interrupt config registers
  97
  98     // cpu memory addresses
  99     enum {
 100         GICC_CTLR  = 0x00, // CPU control register
 101         GICC_PMR   = 0x04, // Interrupt priority mask
 102         GICC_BPR   = 0x08, // binary point register
 103         GICC_IAR   = 0x0C, // interrupt ack register
 104         GICC_EOIR  = 0x10, // end of interrupt
 105         GICC_RPR   = 0x14, // running priority
 106         GICC_HPPIR = 0x18, // highest pending interrupt
 107         GICC_ABPR  = 0x1c, // aliased binary point
 108         GICC_IIDR  = 0xfc, // cpu interface id register
 109
 110         CPU_SIZE   = 0xff
 111     };
 112
 113     static const int SGI_MAX = 16;  // Number of Software Gen Interrupts
 114     static const int PPI_MAX = 16;  // Number of Private Peripheral Interrupts
 115
 116     /** Mask off SGI's when setting/clearing pending bits */
 117     static const int SGI_MASK = 0xFFFF0000;
 118
 119     /** Mask for bits that config N:N mode in GICD_ICFGR's */
 120     static const int NN_CONFIG_MASK = 0x55555555;
 121
 122     static const int CPU_MAX = 256;   // Max number of supported CPU interfaces
 123     static const int SPURIOUS_INT = 1023;
 124     static const int INT_BITS_MAX = 32;
 125     static const int INT_LINES_MAX = 1020;
 126     static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
 127
 128     /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
 129         chosen for consistency with Linux's in-kernel KVM GIC model */
 130     static const int GICC_BPR_MINIMUM = 2;
 131
 132     BitUnion32(SWI)
 133         Bitfield<3,0> sgi_id;
 134         Bitfield<23,16> cpu_list;
 135         Bitfield<25,24> list_type;
 136     EndBitUnion(SWI)
 137
 138     BitUnion32(IAR)
 139         Bitfield<9,0> ack_id;
 140         Bitfield<12,10> cpu_id;
 141     EndBitUnion(IAR)
 142
 143   protected: /* Params */
 144     /** Address range for the distributor interface */
 145     const AddrRange distRange;
 146
 147     /** Address range for the CPU interfaces */
 148     const AddrRange cpuRange;
 149
 150     /** All address ranges used by this GIC */
 151     const AddrRangeList addrRanges;
 152
 153     /** Latency for a distributor operation */
 154     const Tick distPioDelay;
 155
 156     /** Latency for a cpu operation */
 157     const Tick cpuPioDelay;
 158
 159     /** Latency for a interrupt to get to CPU */
 160     const Tick intLatency;
 161
 162   protected:
 163     /** Gic enabled */
 164     bool enabled;
 165
 166     /** Are gem5 extensions available? */
 167     const bool haveGem5Extensions;
 168
 169     /** gem5 many-core extension enabled by driver */
 170     bool gem5ExtensionsEnabled;
 171
 172     /** Number of itLines enabled */
 173     uint32_t itLines;
 174
 175     /** Registers "banked for each connected processor" per ARM IHI0048B */
 176     struct BankedRegs : public Serializable {
 177         /** GICD_I{S,C}ENABLER0
 178          * interrupt enable bits for first 32 interrupts, 1b per interrupt */
 179         uint32_t intEnabled;
 180
 181         /** GICD_I{S,C}PENDR0
 182          * interrupt pending bits for first 32 interrupts, 1b per interrupt */
 183         uint32_t pendingInt;
 184
 185         /** GICD_I{S,C}ACTIVER0
 186          * interrupt active bits for first 32 interrupts, 1b per interrupt */
 187         uint32_t activeInt;
 188
 189         /** GICD_IPRIORITYR{0..7}
 190          * interrupt priority for SGIs and PPIs */
 191         uint8_t intPriority[SGI_MAX + PPI_MAX];
 192
 193         void serialize(CheckpointOut &cp) const override;
 194         void unserialize(CheckpointIn &cp) override;
 195
 196         BankedRegs() :
 197             intEnabled(0), pendingInt(0), activeInt(0), intPriority {0}
 198           {}
 199     };
 200     std::vector<BankedRegs*> bankedRegs;
 201
 202     BankedRegs& getBankedRegs(ContextID);
 203
 204     /** GICD_I{S,C}ENABLER{1..31}
 205      * interrupt enable bits for global interrupts
 206      * 1b per interrupt, 32 bits per word, 31 words */
 207     uint32_t intEnabled[INT_BITS_MAX-1];
 208
 209     uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
 210         if (ix == 0) {
 211             return getBankedRegs(ctx).intEnabled;
 212         } else {
 213             return intEnabled[ix - 1];
 214         }
 215     }
 216
 217     /** GICD_I{S,C}PENDR{1..31}
 218      * interrupt pending bits for global interrupts
 219      * 1b per interrupt, 32 bits per word, 31 words */
 220     uint32_t pendingInt[INT_BITS_MAX-1];
 221
 222     uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
 223         assert(ix < INT_BITS_MAX);
 224         if (ix == 0) {
 225             return getBankedRegs(ctx).pendingInt;
 226         } else {
 227             return pendingInt[ix - 1];
 228         }
 229     }
 230
 231     /** GICD_I{S,C}ACTIVER{1..31}
 232      * interrupt active bits for global interrupts
 233      * 1b per interrupt, 32 bits per word, 31 words */
 234     uint32_t activeInt[INT_BITS_MAX-1];
 235
 236     uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
 237         assert(ix < INT_BITS_MAX);
 238         if (ix == 0) {
 239             return getBankedRegs(ctx).activeInt;
 240         } else {
 241             return activeInt[ix - 1];
 242         }
 243     }
 244
 245     /** read only running priority register, 1 per cpu*/
 246     uint32_t iccrpr[CPU_MAX];
 247
 248     /** GICD_IPRIORITYR{8..255}
 249      * an 8 bit priority (lower is higher priority) for each
 250      * of the global (not replicated per CPU) interrupts.
 251      */
 252     uint8_t intPriority[GLOBAL_INT_LINES];
 253
 254     uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
 255         assert(ix < INT_LINES_MAX);
 256         if (ix < SGI_MAX + PPI_MAX) {
 257             return getBankedRegs(ctx).intPriority[ix];
 258         } else {
 259             return intPriority[ix - (SGI_MAX + PPI_MAX)];
 260         }
 261     }
 262
 263     /** GICD_ITARGETSR{8..255}
 264      * an 8 bit cpu target id for each global interrupt.
 265      */
 266     uint8_t cpuTarget[GLOBAL_INT_LINES];
 267
 268     uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
 269         assert(ctx < sys->numRunningContexts());
 270         assert(ix < INT_LINES_MAX);
 271         if (ix < SGI_MAX + PPI_MAX) {
 272             // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
 273             // field returns a value that corresponds only to the processor
 274             // reading the register."
 275             uint32_t ctx_mask;
 276             if (gem5ExtensionsEnabled) {
 277                 ctx_mask = ctx;
 278             } else {
 279             // convert the CPU id number into a bit mask
 280                 ctx_mask = power(2, ctx);
 281             }
 282             return ctx_mask;
 283         } else {
 284             return cpuTarget[ix - 32];
 285         }
 286     }
 287
 288     /** 2 bit per interrupt signaling if it's level or edge sensitive
 289      * and if it is 1:N or N:N */
 290     uint32_t intConfig[INT_BITS_MAX*2];
 291
 292     /** CPU enabled */
 293     bool cpuEnabled[CPU_MAX];
 294
 295     /** CPU priority */
 296     uint8_t cpuPriority[CPU_MAX];
 297     uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
 298
 299     /** Binary point registers */
 300     uint8_t cpuBpr[CPU_MAX];
 301
 302     /** highest interrupt that is interrupting CPU */
 303     uint32_t cpuHighestInt[CPU_MAX];
 304
 305     /** One bit per cpu per software interrupt that is pending for each possible
 306      * sgi source. Indexed by SGI number. Each byte in generating cpu id and
 307      * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
 308      * for CPU 2. */
 309     uint64_t cpuSgiPending[SGI_MAX];
 310     uint64_t cpuSgiActive[SGI_MAX];
 311
 312     /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
 313      * 16 SGI pending bits for each of the (large number of) CPUs.
 314      */
 315     uint32_t cpuSgiPendingExt[CPU_MAX];
 316     uint32_t cpuSgiActiveExt[CPU_MAX];
 317
 318     /** One bit per private peripheral interrupt. Only upper 16 bits
 319      * will be used since PPI interrupts are numberred from 16 to 32 */
 320     uint32_t cpuPpiPending[CPU_MAX];
 321     uint32_t cpuPpiActive[CPU_MAX];
 322
 323     /** software generated interrupt
 324      * @param data data to decode that indicates which cpus to interrupt
 325      */
 326     void softInt(ContextID ctx, SWI swi);
 327
 328     /** See if some processor interrupt flags need to be enabled/disabled
 329      * @param hint which set of interrupts needs to be checked
 330      */
 331     virtual void updateIntState(int hint);
 332
 333     /** Update the register that records priority of the highest priority
 334      *  active interrupt*/
 335     void updateRunPri();
 336
 337     /** generate a bit mask to check cpuSgi for an interrupt. */
 338     uint64_t genSwiMask(int cpu);
 339
 340     int intNumToWord(int num) const { return num >> 5; }
 341     int intNumToBit(int num) const { return num % 32; }
 342
 343     /**
 344      * Post an interrupt to a CPU with a delay
 345      */
 346     void postInt(uint32_t cpu, Tick when);
 347
 348     /**
 349      * Deliver a delayed interrupt to the target CPU
 350      */
 351     void postDelayedInt(uint32_t cpu);
 352
 353     EventFunctionWrapper *postIntEvent[CPU_MAX];
 354     int pendingDelayedInterrupts;
 355
 356   public:
 357     typedef Pl390Params Params;
 358     const Params *
 359     params() const
 360     {
 361         return dynamic_cast<const Params *>(_params);
 362     }
 363     Pl390(const Params *p);
 364     ~Pl390();
 365
 366     DrainState drain() override;
 367     void drainResume() override;
 368
 369     void serialize(CheckpointOut &cp) const override;
 370     void unserialize(CheckpointIn &cp) override;
 371
 372   public: /* PioDevice */
 373     AddrRangeList getAddrRanges() const override { return addrRanges; }
 374
 375     /** A PIO read to the device, immediately split up into
 376      * readDistributor() or readCpu()
 377      */
 378     Tick read(PacketPtr pkt) override;
 379
 380     /** A PIO read to the device, immediately split up into
 381      * writeDistributor() or writeCpu()
 382      */
 383     Tick write(PacketPtr pkt) override;
 384
 385   public: /* BaseGic */
 386     void sendInt(uint32_t number) override;
 387     void clearInt(uint32_t number) override;
 388
 389     void sendPPInt(uint32_t num, uint32_t cpu) override;
 390     void clearPPInt(uint32_t num, uint32_t cpu) override;
 391
 392   protected:
 393     /** Handle a read to the distributor portion of the GIC
 394      * @param pkt packet to respond to
 395      */
 396     Tick readDistributor(PacketPtr pkt);
 397     uint32_t readDistributor(ContextID ctx, Addr daddr,
 398                              size_t resp_sz);
 399     uint32_t readDistributor(ContextID ctx, Addr daddr) override {
 400         return readDistributor(ctx, daddr, 4);
 401     }
 402
 403     /** Handle a read to the cpu portion of the GIC
 404      * @param pkt packet to respond to
 405      */
 406     Tick readCpu(PacketPtr pkt);
 407     uint32_t readCpu(ContextID ctx, Addr daddr) override;
 408
 409     /** Handle a write to the distributor portion of the GIC
 410      * @param pkt packet to respond to
 411      */
 412     Tick writeDistributor(PacketPtr pkt);
 413     void writeDistributor(ContextID ctx, Addr daddr,
 414                           uint32_t data, size_t data_sz);
 415     void writeDistributor(ContextID ctx, Addr daddr,
 416                                   uint32_t data) override {
 417         return writeDistributor(ctx, daddr, data, 4);
 418     }
 419
 420     /** Handle a write to the cpu portion of the GIC
 421      * @param pkt packet to respond to
 422      */
 423     Tick writeCpu(PacketPtr pkt);
 424     void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
 425 };
 426
 427 #endif //__DEV_ARM_GIC_H__