src/dev/arm/gic_pl390.hh

   1 /*
   2  * Copyright (c) 2010, 2013, 2015-2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43
  44 /** @file
  45  * Implementation of a PL390 GIC
  46  */
  47
  48 #ifndef __DEV_ARM_GIC_PL390_H__
  49 #define __DEV_ARM_GIC_PL390_H__
  50
  51 #include <vector>
  52
  53 #include "base/addr_range.hh"
  54 #include "base/bitunion.hh"
  55 #include "cpu/intr_control.hh"
  56 #include "dev/arm/base_gic.hh"
  57 #include "dev/io_device.hh"
  58 #include "dev/platform.hh"
  59 #include "params/Pl390.hh"
  60
  61 class Pl390 : public BaseGic
  62 {
  63   protected:
  64     // distributor memory addresses
  65     enum {
  66         GICD_CTLR          = 0x000, // control register
  67         GICD_TYPER         = 0x004, // controller type
  68         GICD_IIDR          = 0x008, // implementer id
  69         GICD_SGIR          = 0xf00, // software generated interrupt
  70
  71         DIST_SIZE          = 0xfff
  72     };
  73
  74     static const AddrRange GICD_ISENABLER;  // interrupt set enable
  75     static const AddrRange GICD_ICENABLER;  // interrupt clear enable
  76     static const AddrRange GICD_ISPENDR;    // set pending interrupt
  77     static const AddrRange GICD_ICPENDR;    // clear pending interrupt
  78     static const AddrRange GICD_ISACTIVER;  // active bit registers
  79     static const AddrRange GICD_ICACTIVER;  // clear bit registers
  80     static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
  81     static const AddrRange GICD_ITARGETSR;  // processor target registers
  82     static const AddrRange GICD_ICFGR;      // interrupt config registers
  83
  84     // cpu memory addresses
  85     enum {
  86         GICC_CTLR  = 0x00, // CPU control register
  87         GICC_PMR   = 0x04, // Interrupt priority mask
  88         GICC_BPR   = 0x08, // binary point register
  89         GICC_IAR   = 0x0C, // interrupt ack register
  90         GICC_EOIR  = 0x10, // end of interrupt
  91         GICC_RPR   = 0x14, // running priority
  92         GICC_HPPIR = 0x18, // highest pending interrupt
  93         GICC_ABPR  = 0x1c, // aliased binary point
  94         GICC_IIDR  = 0xfc, // cpu interface id register
  95
  96         CPU_SIZE   = 0xff
  97     };
  98
  99     static const int SGI_MAX = 16;  // Number of Software Gen Interrupts
 100     static const int PPI_MAX = 16;  // Number of Private Peripheral Interrupts
 101
 102     /** Mask off SGI's when setting/clearing pending bits */
 103     static const int SGI_MASK = 0xFFFF0000;
 104
 105     /** Mask for bits that config N:N mode in GICD_ICFGR's */
 106     static const int NN_CONFIG_MASK = 0x55555555;
 107
 108     static const int CPU_MAX = 256;   // Max number of supported CPU interfaces
 109     static const int SPURIOUS_INT = 1023;
 110     static const int INT_BITS_MAX = 32;
 111     static const int INT_LINES_MAX = 1020;
 112     static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
 113
 114     BitUnion32(SWI)
 115         Bitfield<3,0> sgi_id;
 116         Bitfield<23,16> cpu_list;
 117         Bitfield<25,24> list_type;
 118     EndBitUnion(SWI)
 119
 120     BitUnion32(IAR)
 121         Bitfield<9,0> ack_id;
 122         Bitfield<12,10> cpu_id;
 123     EndBitUnion(IAR)
 124
 125   protected: /* Params */
 126     /** Address range for the distributor interface */
 127     const AddrRange distRange;
 128
 129     /** Address range for the CPU interfaces */
 130     const AddrRange cpuRange;
 131
 132     /** All address ranges used by this GIC */
 133     const AddrRangeList addrRanges;
 134
 135     /** Latency for a distributor operation */
 136     const Tick distPioDelay;
 137
 138     /** Latency for a cpu operation */
 139     const Tick cpuPioDelay;
 140
 141     /** Latency for a interrupt to get to CPU */
 142     const Tick intLatency;
 143
 144   protected:
 145     /** Gic enabled */
 146     bool enabled;
 147
 148     /** Are gem5 extensions available? */
 149     const bool haveGem5Extensions;
 150
 151     /** gem5 many-core extension enabled by driver */
 152     bool gem5ExtensionsEnabled;
 153
 154     /** Number of itLines enabled */
 155     uint32_t itLines;
 156
 157     /** Registers "banked for each connected processor" per ARM IHI0048B */
 158     struct BankedRegs : public Serializable {
 159         /** GICD_I{S,C}ENABLER0
 160          * interrupt enable bits for first 32 interrupts, 1b per interrupt */
 161         uint32_t intEnabled;
 162
 163         /** GICD_I{S,C}PENDR0
 164          * interrupt pending bits for first 32 interrupts, 1b per interrupt */
 165         uint32_t pendingInt;
 166
 167         /** GICD_I{S,C}ACTIVER0
 168          * interrupt active bits for first 32 interrupts, 1b per interrupt */
 169         uint32_t activeInt;
 170
 171         /** GICD_IPRIORITYR{0..7}
 172          * interrupt priority for SGIs and PPIs */
 173         uint8_t intPriority[SGI_MAX + PPI_MAX];
 174
 175         /** GICD_ITARGETSR{0..7}
 176          * 8b CPU target ID for each SGI and PPI */
 177         uint8_t cpuTarget[SGI_MAX + PPI_MAX];
 178
 179         void serialize(CheckpointOut &cp) const override;
 180         void unserialize(CheckpointIn &cp) override;
 181
 182         BankedRegs() :
 183             intEnabled(0), pendingInt(0), activeInt(0),
 184             intPriority {0}, cpuTarget {0}
 185           {}
 186     };
 187     std::vector<BankedRegs*> bankedRegs;
 188
 189     BankedRegs& getBankedRegs(ContextID);
 190
 191     /** GICD_I{S,C}ENABLER{1..31}
 192      * interrupt enable bits for global interrupts
 193      * 1b per interrupt, 32 bits per word, 31 words */
 194     uint32_t intEnabled[INT_BITS_MAX-1];
 195
 196     uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
 197         if (ix == 0) {
 198             return getBankedRegs(ctx).intEnabled;
 199         } else {
 200             return intEnabled[ix - 1];
 201         }
 202     }
 203
 204     /** GICD_I{S,C}PENDR{1..31}
 205      * interrupt pending bits for global interrupts
 206      * 1b per interrupt, 32 bits per word, 31 words */
 207     uint32_t pendingInt[INT_BITS_MAX-1];
 208
 209     uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
 210         assert(ix < INT_BITS_MAX);
 211         if (ix == 0) {
 212             return getBankedRegs(ctx).pendingInt;
 213         } else {
 214             return pendingInt[ix - 1];
 215         }
 216     }
 217
 218     /** GICD_I{S,C}ACTIVER{1..31}
 219      * interrupt active bits for global interrupts
 220      * 1b per interrupt, 32 bits per word, 31 words */
 221     uint32_t activeInt[INT_BITS_MAX-1];
 222
 223     uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
 224         assert(ix < INT_BITS_MAX);
 225         if (ix == 0) {
 226             return getBankedRegs(ctx).activeInt;
 227         } else {
 228             return activeInt[ix - 1];
 229         }
 230     }
 231
 232     /** read only running priority register, 1 per cpu*/
 233     uint32_t iccrpr[CPU_MAX];
 234
 235     /** GICD_IPRIORITYR{8..255}
 236      * an 8 bit priority (lower is higher priority) for each
 237      * of the global (not replicated per CPU) interrupts.
 238      */
 239     uint8_t intPriority[GLOBAL_INT_LINES];
 240
 241     uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
 242         assert(ix < INT_LINES_MAX);
 243         if (ix < SGI_MAX + PPI_MAX) {
 244             return getBankedRegs(ctx).intPriority[ix];
 245         } else {
 246             return intPriority[ix - (SGI_MAX + PPI_MAX)];
 247         }
 248     }
 249
 250     /** GICD_ITARGETSR{8..255}
 251      * an 8 bit cpu target id for each global interrupt.
 252      */
 253     uint8_t cpuTarget[GLOBAL_INT_LINES];
 254
 255     uint8_t& getCpuTarget(ContextID ctx, uint32_t ix) {
 256         assert(ix < INT_LINES_MAX);
 257         if (ix < SGI_MAX + PPI_MAX) {
 258             return getBankedRegs(ctx).cpuTarget[ix];
 259         } else {
 260             return cpuTarget[ix - (SGI_MAX + PPI_MAX)];
 261         }
 262     }
 263
 264     /** 2 bit per interrupt signaling if it's level or edge sensitive
 265      * and if it is 1:N or N:N */
 266     uint32_t intConfig[INT_BITS_MAX*2];
 267
 268     /** CPU enabled */
 269     bool cpuEnabled[CPU_MAX];
 270
 271     /** CPU priority */
 272     uint8_t cpuPriority[CPU_MAX];
 273
 274     /** Binary point registers */
 275     uint8_t cpuBpr[CPU_MAX];
 276
 277     /** highest interrupt that is interrupting CPU */
 278     uint32_t cpuHighestInt[CPU_MAX];
 279
 280     /** One bit per cpu per software interrupt that is pending for each possible
 281      * sgi source. Indexed by SGI number. Each byte in generating cpu id and
 282      * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
 283      * for CPU 2. */
 284     uint64_t cpuSgiPending[SGI_MAX];
 285     uint64_t cpuSgiActive[SGI_MAX];
 286
 287     /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
 288      * 16 SGI pending bits for each of the (large number of) CPUs.
 289      */
 290     uint32_t cpuSgiPendingExt[CPU_MAX];
 291     uint32_t cpuSgiActiveExt[CPU_MAX];
 292
 293     /** One bit per private peripheral interrupt. Only upper 16 bits
 294      * will be used since PPI interrupts are numberred from 16 to 32 */
 295     uint32_t cpuPpiPending[CPU_MAX];
 296     uint32_t cpuPpiActive[CPU_MAX];
 297
 298     /** IRQ Enable Used for debug */
 299     bool irqEnable;
 300
 301     /** software generated interrupt
 302      * @param data data to decode that indicates which cpus to interrupt
 303      */
 304     void softInt(ContextID ctx, SWI swi);
 305
 306     /** See if some processor interrupt flags need to be enabled/disabled
 307      * @param hint which set of interrupts needs to be checked
 308      */
 309     void updateIntState(int hint);
 310
 311     /** Update the register that records priority of the highest priority
 312      *  active interrupt*/
 313     void updateRunPri();
 314
 315     /** generate a bit mask to check cpuSgi for an interrupt. */
 316     uint64_t genSwiMask(int cpu);
 317
 318     int intNumToWord(int num) const { return num >> 5; }
 319     int intNumToBit(int num) const { return num % 32; }
 320
 321     /**
 322      * Post an interrupt to a CPU with a delay
 323      */
 324     void postInt(uint32_t cpu, Tick when);
 325
 326     /**
 327      * Deliver a delayed interrupt to the target CPU
 328      */
 329     void postDelayedInt(uint32_t cpu);
 330
 331     /** Event definition to post interrupt to CPU after a delay
 332     */
 333     class PostIntEvent : public Event
 334     {
 335       private:
 336         Pl390 &parent;
 337         uint32_t cpu;
 338       public:
 339         PostIntEvent(Pl390 &_parent, uint32_t _cpu)
 340             : parent(_parent), cpu(_cpu)
 341         { }
 342         void process() { parent.postDelayedInt(cpu); }
 343         const char *description() const { return "Post Interrupt to CPU"; }
 344     };
 345     PostIntEvent *postIntEvent[CPU_MAX];
 346     int pendingDelayedInterrupts;
 347
 348   public:
 349     typedef Pl390Params Params;
 350     const Params *
 351     params() const
 352     {
 353         return dynamic_cast<const Params *>(_params);
 354     }
 355     Pl390(const Params *p);
 356
 357     DrainState drain() override;
 358
 359     void serialize(CheckpointOut &cp) const override;
 360     void unserialize(CheckpointIn &cp) override;
 361
 362   public: /* PioDevice */
 363     AddrRangeList getAddrRanges() const override { return addrRanges; }
 364
 365     /** A PIO read to the device, immediately split up into
 366      * readDistributor() or readCpu()
 367      */
 368     Tick read(PacketPtr pkt) override;
 369
 370     /** A PIO read to the device, immediately split up into
 371      * writeDistributor() or writeCpu()
 372      */
 373     Tick write(PacketPtr pkt) override;
 374
 375   public: /* BaseGic */
 376     void sendInt(uint32_t number) override;
 377     void clearInt(uint32_t number) override;
 378
 379     void sendPPInt(uint32_t num, uint32_t cpu) override;
 380     void clearPPInt(uint32_t num, uint32_t cpu) override;
 381
 382   public: // Test & debug intefaces
 383     /** @{ */
 384     /* Various functions fer testing and debugging */
 385     void driveSPI(uint32_t spi);
 386     void driveLegIRQ(bool state);
 387     void driveLegFIQ(bool state);
 388     void driveIrqEn(bool state);
 389     /** @} */
 390
 391   protected:
 392     /** Handle a read to the distributor portion of the GIC
 393      * @param pkt packet to respond to
 394      */
 395     Tick readDistributor(PacketPtr pkt);
 396     uint32_t readDistributor(ContextID ctx, Addr daddr, size_t resp_sz);
 397
 398     /** Handle a read to the cpu portion of the GIC
 399      * @param pkt packet to respond to
 400      */
 401     Tick readCpu(PacketPtr pkt);
 402     uint32_t readCpu(ContextID ctx, Addr daddr);
 403
 404     /** Handle a write to the distributor portion of the GIC
 405      * @param pkt packet to respond to
 406      */
 407     Tick writeDistributor(PacketPtr pkt);
 408     void writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
 409                           size_t data_sz);
 410
 411     /** Handle a write to the cpu portion of the GIC
 412      * @param pkt packet to respond to
 413      */
 414     Tick writeCpu(PacketPtr pkt);
 415     void writeCpu(ContextID ctx, Addr daddr, uint32_t data);
 416 };
 417
 418 #endif //__DEV_ARM_GIC_H__