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45 * Implementation of a PL390 GIC
48 #ifndef __DEV_ARM_GIC_PL390_H__
49 #define __DEV_ARM_GIC_PL390_H__
53 #include "base/addr_range.hh"
54 #include "base/bitunion.hh"
55 #include "cpu/intr_control.hh"
56 #include "dev/arm/base_gic.hh"
57 #include "dev/io_device.hh"
58 #include "dev/platform.hh"
59 #include "params/Pl390.hh"
61 class Pl390 : public BaseGic
64 // distributor memory addresses
66 GICD_CTLR = 0x000, // control register
67 GICD_TYPER = 0x004, // controller type
68 GICD_IIDR = 0x008, // implementer id
69 GICD_SGIR = 0xf00, // software generated interrupt
74 static const AddrRange GICD_ISENABLER; // interrupt set enable
75 static const AddrRange GICD_ICENABLER; // interrupt clear enable
76 static const AddrRange GICD_ISPENDR; // set pending interrupt
77 static const AddrRange GICD_ICPENDR; // clear pending interrupt
78 static const AddrRange GICD_ISACTIVER; // active bit registers
79 static const AddrRange GICD_ICACTIVER; // clear bit registers
80 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
81 static const AddrRange GICD_ITARGETSR; // processor target registers
82 static const AddrRange GICD_ICFGR; // interrupt config registers
84 // cpu memory addresses
86 GICC_CTLR = 0x00, // CPU control register
87 GICC_PMR = 0x04, // Interrupt priority mask
88 GICC_BPR = 0x08, // binary point register
89 GICC_IAR = 0x0C, // interrupt ack register
90 GICC_EOIR = 0x10, // end of interrupt
91 GICC_RPR = 0x14, // running priority
92 GICC_HPPIR = 0x18, // highest pending interrupt
93 GICC_ABPR = 0x1c, // aliased binary point
94 GICC_IIDR = 0xfc, // cpu interface id register
99 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
100 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
102 /** Mask off SGI's when setting/clearing pending bits */
103 static const int SGI_MASK = 0xFFFF0000;
105 /** Mask for bits that config N:N mode in GICD_ICFGR's */
106 static const int NN_CONFIG_MASK = 0x55555555;
108 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
109 static const int SPURIOUS_INT = 1023;
110 static const int INT_BITS_MAX = 32;
111 static const int INT_LINES_MAX = 1020;
112 static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
115 Bitfield<3,0> sgi_id;
116 Bitfield<23,16> cpu_list;
117 Bitfield<25,24> list_type;
121 Bitfield<9,0> ack_id;
122 Bitfield<12,10> cpu_id;
125 /** Distributor address GIC listens at */
128 /** CPU address GIC listens at */
129 /** @todo is this one per cpu? */
132 /** Latency for a distributor operation */
135 /** Latency for a cpu operation */
138 /** Latency for a interrupt to get to CPU */
144 /** Are gem5 extensions available? */
145 const bool haveGem5Extensions;
147 /** gem5 many-core extension enabled by driver */
148 bool gem5ExtensionsEnabled;
150 /** Number of itLines enabled */
153 /** Registers "banked for each connected processor" per ARM IHI0048B */
154 struct BankedRegs : public Serializable {
155 /** GICD_I{S,C}ENABLER0
156 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
159 /** GICD_I{S,C}PENDR0
160 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
163 /** GICD_I{S,C}ACTIVER0
164 * interrupt active bits for first 32 interrupts, 1b per interrupt */
167 /** GICD_IPRIORITYR{0..7}
168 * interrupt priority for SGIs and PPIs */
169 uint8_t intPriority[SGI_MAX + PPI_MAX];
171 /** GICD_ITARGETSR{0..7}
172 * 8b CPU target ID for each SGI and PPI */
173 uint8_t cpuTarget[SGI_MAX + PPI_MAX];
175 void serialize(CheckpointOut &cp) const override;
176 void unserialize(CheckpointIn &cp) override;
179 intEnabled(0), pendingInt(0), activeInt(0),
180 intPriority {0}, cpuTarget {0}
183 std::vector<BankedRegs*> bankedRegs;
185 BankedRegs& getBankedRegs(ContextID);
187 /** GICD_I{S,C}ENABLER{1..31}
188 * interrupt enable bits for global interrupts
189 * 1b per interrupt, 32 bits per word, 31 words */
190 uint32_t intEnabled[INT_BITS_MAX-1];
192 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
194 return getBankedRegs(ctx).intEnabled;
196 return intEnabled[ix - 1];
200 /** GICD_I{S,C}PENDR{1..31}
201 * interrupt pending bits for global interrupts
202 * 1b per interrupt, 32 bits per word, 31 words */
203 uint32_t pendingInt[INT_BITS_MAX-1];
205 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
206 assert(ix < INT_BITS_MAX);
208 return getBankedRegs(ctx).pendingInt;
210 return pendingInt[ix - 1];
214 /** GICD_I{S,C}ACTIVER{1..31}
215 * interrupt active bits for global interrupts
216 * 1b per interrupt, 32 bits per word, 31 words */
217 uint32_t activeInt[INT_BITS_MAX-1];
219 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
220 assert(ix < INT_BITS_MAX);
222 return getBankedRegs(ctx).activeInt;
224 return activeInt[ix - 1];
228 /** read only running priority register, 1 per cpu*/
229 uint32_t iccrpr[CPU_MAX];
231 /** GICD_IPRIORITYR{8..255}
232 * an 8 bit priority (lower is higher priority) for each
233 * of the global (not replicated per CPU) interrupts.
235 uint8_t intPriority[GLOBAL_INT_LINES];
237 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
238 assert(ix < INT_LINES_MAX);
239 if (ix < SGI_MAX + PPI_MAX) {
240 return getBankedRegs(ctx).intPriority[ix];
242 return intPriority[ix - (SGI_MAX + PPI_MAX)];
246 /** GICD_ITARGETSR{8..255}
247 * an 8 bit cpu target id for each global interrupt.
249 uint8_t cpuTarget[GLOBAL_INT_LINES];
251 uint8_t& getCpuTarget(ContextID ctx, uint32_t ix) {
252 assert(ix < INT_LINES_MAX);
253 if (ix < SGI_MAX + PPI_MAX) {
254 return getBankedRegs(ctx).cpuTarget[ix];
256 return cpuTarget[ix - (SGI_MAX + PPI_MAX)];
260 /** 2 bit per interrupt signaling if it's level or edge sensitive
261 * and if it is 1:N or N:N */
262 uint32_t intConfig[INT_BITS_MAX*2];
265 bool cpuEnabled[CPU_MAX];
268 uint8_t cpuPriority[CPU_MAX];
270 /** Binary point registers */
271 uint8_t cpuBpr[CPU_MAX];
273 /** highest interrupt that is interrupting CPU */
274 uint32_t cpuHighestInt[CPU_MAX];
276 /** One bit per cpu per software interrupt that is pending for each possible
277 * sgi source. Indexed by SGI number. Each byte in generating cpu id and
278 * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
280 uint64_t cpuSgiPending[SGI_MAX];
281 uint64_t cpuSgiActive[SGI_MAX];
283 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
284 * 16 SGI pending bits for each of the (large number of) CPUs.
286 uint32_t cpuSgiPendingExt[CPU_MAX];
287 uint32_t cpuSgiActiveExt[CPU_MAX];
289 /** One bit per private peripheral interrupt. Only upper 16 bits
290 * will be used since PPI interrupts are numberred from 16 to 32 */
291 uint32_t cpuPpiPending[CPU_MAX];
292 uint32_t cpuPpiActive[CPU_MAX];
294 /** IRQ Enable Used for debug */
297 /** software generated interrupt
298 * @param data data to decode that indicates which cpus to interrupt
300 void softInt(ContextID ctx, SWI swi);
302 /** See if some processor interrupt flags need to be enabled/disabled
303 * @param hint which set of interrupts needs to be checked
305 void updateIntState(int hint);
307 /** Update the register that records priority of the highest priority
311 /** generate a bit mask to check cpuSgi for an interrupt. */
312 uint64_t genSwiMask(int cpu);
314 int intNumToWord(int num) const { return num >> 5; }
315 int intNumToBit(int num) const { return num % 32; }
317 /** Post an interrupt to a CPU
319 void postInt(uint32_t cpu, Tick when);
321 /** Event definition to post interrupt to CPU after a delay
323 class PostIntEvent : public Event
329 PostIntEvent( uint32_t c, Platform* p)
330 : cpu(c), platform(p)
332 void process() { platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);}
333 const char *description() const { return "Post Interrupt to CPU"; }
335 PostIntEvent *postIntEvent[CPU_MAX];
338 typedef Pl390Params Params;
342 return dynamic_cast<const Params *>(_params);
344 Pl390(const Params *p);
347 /** Return the address ranges used by the Gic
348 * This is the distributor address + all cpu addresses
350 AddrRangeList getAddrRanges() const override;
352 /** A PIO read to the device, immediately split up into
353 * readDistributor() or readCpu()
355 Tick read(PacketPtr pkt) override;
357 /** A PIO read to the device, immediately split up into
358 * writeDistributor() or writeCpu()
360 Tick write(PacketPtr pkt) override;
364 /** Post an interrupt from a device that is connected to the Gic.
365 * Depending on the configuration, the gic will pass this interrupt
366 * on through to a CPU.
367 * @param number number of interrupt to send */
368 void sendInt(uint32_t number) override;
370 /** Interface call for private peripheral interrupts */
371 void sendPPInt(uint32_t num, uint32_t cpu) override;
373 /** Clear an interrupt from a device that is connected to the Gic
374 * Depending on the configuration, the gic may de-assert it's cpu line
375 * @param number number of interrupt to send */
376 void clearInt(uint32_t number) override;
378 /** Clear a (level-sensitive) PPI */
379 void clearPPInt(uint32_t num, uint32_t cpu) override;
383 /* Various functions fer testing and debugging */
384 void driveSPI(uint32_t spi);
385 void driveLegIRQ(bool state);
386 void driveLegFIQ(bool state);
387 void driveIrqEn(bool state);
390 void serialize(CheckpointOut &cp) const override;
391 void unserialize(CheckpointIn &cp) override;
394 /** Handle a read to the distributor portion of the GIC
395 * @param pkt packet to respond to
397 Tick readDistributor(PacketPtr pkt);
399 /** Handle a read to the cpu portion of the GIC
400 * @param pkt packet to respond to
402 Tick readCpu(PacketPtr pkt);
404 /** Handle a write to the distributor portion of the GIC
405 * @param pkt packet to respond to
407 Tick writeDistributor(PacketPtr pkt);
409 /** Handle a write to the cpu portion of the GIC
410 * @param pkt packet to respond to
412 Tick writeCpu(PacketPtr pkt);
415 #endif //__DEV_ARM_GIC_H__