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45 * Implementation of a GICv2
48 #ifndef __DEV_ARM_GICV2_H__
49 #define __DEV_ARM_GICV2_H__
53 #include "base/addr_range.hh"
54 #include "base/bitunion.hh"
55 #include "cpu/intr_control.hh"
56 #include "dev/arm/base_gic.hh"
57 #include "dev/io_device.hh"
58 #include "dev/platform.hh"
59 #include "params/GicV2.hh"
61 class GicV2 : public BaseGic, public BaseGicRegisters
64 // distributor memory addresses
66 GICD_CTLR = 0x000, // control register
67 GICD_TYPER = 0x004, // controller type
68 GICD_IIDR = 0x008, // implementer id
69 GICD_SGIR = 0xf00, // software generated interrupt
70 GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
71 GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
72 GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
73 GICD_PIDR3 = 0xfec, // distributor peripheral ID3
78 const uint32_t gicdPIDR;
79 const uint32_t gicdIIDR;
80 const uint32_t giccIIDR;
82 static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
83 static const AddrRange GICD_ISENABLER; // interrupt set enable
84 static const AddrRange GICD_ICENABLER; // interrupt clear enable
85 static const AddrRange GICD_ISPENDR; // set pending interrupt
86 static const AddrRange GICD_ICPENDR; // clear pending interrupt
87 static const AddrRange GICD_ISACTIVER; // active bit registers
88 static const AddrRange GICD_ICACTIVER; // clear bit registers
89 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
90 static const AddrRange GICD_ITARGETSR; // processor target registers
91 static const AddrRange GICD_ICFGR; // interrupt config registers
93 // cpu memory addresses
95 GICC_CTLR = 0x00, // CPU control register
96 GICC_PMR = 0x04, // Interrupt priority mask
97 GICC_BPR = 0x08, // binary point register
98 GICC_IAR = 0x0C, // interrupt ack register
99 GICC_EOIR = 0x10, // end of interrupt
100 GICC_RPR = 0x14, // running priority
101 GICC_HPPIR = 0x18, // highest pending interrupt
102 GICC_ABPR = 0x1c, // aliased binary point
103 GICC_APR0 = 0xd0, // active priority register 0
104 GICC_APR1 = 0xd4, // active priority register 1
105 GICC_APR2 = 0xd8, // active priority register 2
106 GICC_APR3 = 0xdc, // active priority register 3
107 GICC_IIDR = 0xfc, // cpu interface id register
108 GICC_DIR = 0x1000, // deactive interrupt register
111 static const int SGI_MAX = 16; // Number of Software Gen Interrupts
112 static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
114 /** Mask off SGI's when setting/clearing pending bits */
115 static const int SGI_MASK = 0xFFFF0000;
117 /** Mask for bits that config N:N mode in GICD_ICFGR's */
118 static const int NN_CONFIG_MASK = 0x55555555;
120 static const int CPU_MAX = 256; // Max number of supported CPU interfaces
121 static const int SPURIOUS_INT = 1023;
122 static const int INT_BITS_MAX = 32;
123 static const int INT_LINES_MAX = 1020;
124 static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
126 /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
127 chosen for consistency with Linux's in-kernel KVM GIC model */
128 static const int GICC_BPR_MINIMUM = 2;
131 Bitfield<3,0> sgi_id;
132 Bitfield<23,16> cpu_list;
133 Bitfield<25,24> list_type;
137 Bitfield<9,0> ack_id;
138 Bitfield<12,10> cpu_id;
143 Bitfield<1> enableGrp1;
144 Bitfield<0> enableGrp0;
147 protected: /* Params */
148 /** Address range for the distributor interface */
149 const AddrRange distRange;
151 /** Address range for the CPU interfaces */
152 const AddrRange cpuRange;
154 /** All address ranges used by this GIC */
155 const AddrRangeList addrRanges;
157 /** Latency for a distributor operation */
158 const Tick distPioDelay;
160 /** Latency for a cpu operation */
161 const Tick cpuPioDelay;
163 /** Latency for a interrupt to get to CPU */
164 const Tick intLatency;
170 /** Are gem5 extensions available? */
171 const bool haveGem5Extensions;
173 /** gem5 many-core extension enabled by driver */
174 bool gem5ExtensionsEnabled;
176 /** Number of itLines enabled */
179 /** Registers "banked for each connected processor" per ARM IHI0048B */
180 struct BankedRegs : public Serializable {
181 /** GICD_I{S,C}ENABLER0
182 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
185 /** GICD_I{S,C}PENDR0
186 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
189 /** GICD_I{S,C}ACTIVER0
190 * interrupt active bits for first 32 interrupts, 1b per interrupt */
194 * interrupt group bits for first 32 interrupts, 1b per interrupt */
197 /** GICD_IPRIORITYR{0..7}
198 * interrupt priority for SGIs and PPIs */
199 uint8_t intPriority[SGI_MAX + PPI_MAX];
201 void serialize(CheckpointOut &cp) const override;
202 void unserialize(CheckpointIn &cp) override;
205 intEnabled(0), pendingInt(0), activeInt(0),
206 intGroup(0), intPriority {0}
209 std::vector<BankedRegs*> bankedRegs;
211 BankedRegs& getBankedRegs(ContextID);
213 /** GICD_I{S,C}ENABLER{1..31}
214 * interrupt enable bits for global interrupts
215 * 1b per interrupt, 32 bits per word, 31 words */
216 uint32_t intEnabled[INT_BITS_MAX-1];
218 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
220 return getBankedRegs(ctx).intEnabled;
222 return intEnabled[ix - 1];
226 /** GICD_I{S,C}PENDR{1..31}
227 * interrupt pending bits for global interrupts
228 * 1b per interrupt, 32 bits per word, 31 words */
229 uint32_t pendingInt[INT_BITS_MAX-1];
231 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
232 assert(ix < INT_BITS_MAX);
234 return getBankedRegs(ctx).pendingInt;
236 return pendingInt[ix - 1];
240 /** GICD_I{S,C}ACTIVER{1..31}
241 * interrupt active bits for global interrupts
242 * 1b per interrupt, 32 bits per word, 31 words */
243 uint32_t activeInt[INT_BITS_MAX-1];
245 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
246 assert(ix < INT_BITS_MAX);
248 return getBankedRegs(ctx).activeInt;
250 return activeInt[ix - 1];
254 /** GICD_IGROUPR{1..31}
255 * interrupt group bits for global interrupts
256 * 1b per interrupt, 32 bits per word, 31 words */
257 uint32_t intGroup[INT_BITS_MAX-1];
259 uint32_t& getIntGroup(ContextID ctx, uint32_t ix) {
260 assert(ix < INT_BITS_MAX);
262 return getBankedRegs(ctx).intGroup;
264 return intGroup[ix - 1];
268 /** read only running priority register, 1 per cpu*/
269 uint32_t iccrpr[CPU_MAX];
271 /** GICD_IPRIORITYR{8..255}
272 * an 8 bit priority (lower is higher priority) for each
273 * of the global (not replicated per CPU) interrupts.
275 uint8_t intPriority[GLOBAL_INT_LINES];
277 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
278 assert(ix < INT_LINES_MAX);
279 if (ix < SGI_MAX + PPI_MAX) {
280 return getBankedRegs(ctx).intPriority[ix];
282 return intPriority[ix - (SGI_MAX + PPI_MAX)];
287 * get 2 bit config associated to an interrupt.
289 uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
290 assert(ix < INT_LINES_MAX);
291 const uint8_t cfg_low = intNumToBit(ix * 2);
292 const uint8_t cfg_hi = cfg_low + 1;
293 return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
296 /** GICD_ITARGETSR{8..255}
297 * an 8 bit cpu target id for each global interrupt.
299 uint8_t cpuTarget[GLOBAL_INT_LINES];
301 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
302 assert(ctx < sys->numRunningContexts());
303 assert(ix < INT_LINES_MAX);
304 if (ix < SGI_MAX + PPI_MAX) {
305 // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
306 // field returns a value that corresponds only to the processor
307 // reading the register."
309 if (gem5ExtensionsEnabled) {
312 // convert the CPU id number into a bit mask
313 ctx_mask = power(2, ctx);
317 return cpuTarget[ix - 32];
321 /** 2 bit per interrupt signaling if it's level or edge sensitive
322 * and if it is 1:N or N:N */
323 uint32_t intConfig[INT_BITS_MAX*2];
325 bool isLevelSensitive(ContextID ctx, uint32_t ix) {
326 if (ix == SPURIOUS_INT) {
329 return bits(getIntConfig(ctx, ix), 1) == 0;
333 bool isGroup0(ContextID ctx, uint32_t int_num) {
334 const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
335 return !bits(group_reg, intNumToBit(int_num));
339 * This method checks if an interrupt ID must be signaled or has been
340 * signaled as a FIQ to the cpu. It does that by reading:
342 * 1) GICD_IGROUPR: controls if the interrupt is part of group0 or
343 * group1. Only group0 interrupts can be signaled as FIQs.
345 * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0
346 * interrupts to a target processor using the FIQ or the IRQ signal
348 bool isFiq(ContextID ctx, uint32_t int_num) {
349 const bool is_group0 = isGroup0(ctx, int_num);
350 const bool use_fiq = cpuControl[ctx].fiqEn;
352 if (is_group0 && use_fiq) {
360 * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
362 bool cpuEnabled(ContextID ctx) const {
363 return cpuControl[ctx].enableGrp0 ||
364 cpuControl[ctx].enableGrp1;
368 * CPU interface control register
370 CTLR cpuControl[CPU_MAX];
373 uint8_t cpuPriority[CPU_MAX];
374 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
376 /** Binary point registers */
377 uint8_t cpuBpr[CPU_MAX];
379 /** highest interrupt that is interrupting CPU */
380 uint32_t cpuHighestInt[CPU_MAX];
382 /** One bit per cpu per software interrupt that is pending for each
383 * possible sgi source. Indexed by SGI number. Each byte in generating cpu
384 * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated
385 * interrupt for CPU 2. */
386 uint64_t cpuSgiPending[SGI_MAX];
387 uint64_t cpuSgiActive[SGI_MAX];
389 /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
390 * 16 SGI pending bits for each of the (large number of) CPUs.
392 uint32_t cpuSgiPendingExt[CPU_MAX];
393 uint32_t cpuSgiActiveExt[CPU_MAX];
395 /** One bit per private peripheral interrupt. Only upper 16 bits
396 * will be used since PPI interrupts are numberred from 16 to 32 */
397 uint32_t cpuPpiPending[CPU_MAX];
398 uint32_t cpuPpiActive[CPU_MAX];
400 /** software generated interrupt
401 * @param data data to decode that indicates which cpus to interrupt
403 void softInt(ContextID ctx, SWI swi);
405 /** See if some processor interrupt flags need to be enabled/disabled
406 * @param hint which set of interrupts needs to be checked
408 virtual void updateIntState(int hint);
410 /** Update the register that records priority of the highest priority
414 /** generate a bit mask to check cpuSgi for an interrupt. */
415 uint64_t genSwiMask(int cpu);
417 int intNumToWord(int num) const { return num >> 5; }
418 int intNumToBit(int num) const { return num % 32; }
420 /** Clears a cpu IRQ or FIQ signal */
421 void clearInt(ContextID ctx, uint32_t int_num);
424 * Post an interrupt to a CPU with a delay
426 void postInt(uint32_t cpu, Tick when);
427 void postFiq(uint32_t cpu, Tick when);
430 * Deliver a delayed interrupt to the target CPU
432 void postDelayedInt(uint32_t cpu);
433 void postDelayedFiq(uint32_t cpu);
435 EventFunctionWrapper *postIntEvent[CPU_MAX];
436 EventFunctionWrapper *postFiqEvent[CPU_MAX];
437 int pendingDelayedInterrupts;
440 typedef GicV2Params Params;
444 return dynamic_cast<const Params *>(_params);
446 GicV2(const Params *p);
449 DrainState drain() override;
450 void drainResume() override;
452 void serialize(CheckpointOut &cp) const override;
453 void unserialize(CheckpointIn &cp) override;
455 public: /* PioDevice */
456 AddrRangeList getAddrRanges() const override { return addrRanges; }
458 /** A PIO read to the device, immediately split up into
459 * readDistributor() or readCpu()
461 Tick read(PacketPtr pkt) override;
463 /** A PIO read to the device, immediately split up into
464 * writeDistributor() or writeCpu()
466 Tick write(PacketPtr pkt) override;
468 public: /* BaseGic */
469 void sendInt(uint32_t number) override;
470 void clearInt(uint32_t number) override;
472 void sendPPInt(uint32_t num, uint32_t cpu) override;
473 void clearPPInt(uint32_t num, uint32_t cpu) override;
476 /** Handle a read to the distributor portion of the GIC
477 * @param pkt packet to respond to
479 Tick readDistributor(PacketPtr pkt);
480 uint32_t readDistributor(ContextID ctx, Addr daddr,
482 uint32_t readDistributor(ContextID ctx, Addr daddr) override {
483 return readDistributor(ctx, daddr, 4);
486 /** Handle a read to the cpu portion of the GIC
487 * @param pkt packet to respond to
489 Tick readCpu(PacketPtr pkt);
490 uint32_t readCpu(ContextID ctx, Addr daddr) override;
492 /** Handle a write to the distributor portion of the GIC
493 * @param pkt packet to respond to
495 Tick writeDistributor(PacketPtr pkt);
496 void writeDistributor(ContextID ctx, Addr daddr,
497 uint32_t data, size_t data_sz);
498 void writeDistributor(ContextID ctx, Addr daddr,
499 uint32_t data) override {
500 return writeDistributor(ctx, daddr, data, 4);
503 /** Handle a write to the cpu portion of the GIC
504 * @param pkt packet to respond to
506 Tick writeCpu(PacketPtr pkt);
507 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
510 #endif //__DEV_ARM_GIC_H__