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41 * Implementiation of a GICv2m MSI shim.
43 * This shim adds MSI support to GICv2.
45 * This should be instantiated with the appropriate number of frames,
46 * and SPI numbers thereof, to the system being modelled.
48 * For example, in RealView.py (or whichever board setup is used), instantiate:
50 * gicv2m = Gicv2m(frames=[
51 * Gicv2mFrame(addr=0x12340000, spi_base=320, spi_len=64),
52 * Gicv2mFrame(addr=0x12350000, spi_base=100, spi_len=32),
53 * Gicv2mFrame(addr=0x12360000, spi_base=150, spi_len=16),
54 * Gicv2mFrame(addr=0x12370000, spi_base=190, spi_len=8),
59 #include "dev/arm/gic_v2m.hh"
61 #include "base/bitunion.hh"
62 #include "base/intmath.hh"
63 #include "debug/Checkpoint.hh"
64 #include "debug/GICV2M.hh"
65 #include "dev/io_device.hh"
66 #include "mem/packet.hh"
67 #include "mem/packet_access.hh"
70 Gicv2mParams::create()
72 return new Gicv2m(this);
76 Gicv2mFrameParams::create()
78 return new Gicv2mFrame(this);
81 Gicv2m::Gicv2m(const Params
*p
)
82 : PioDevice(p
), pioDelay(p
->pio_delay
), frames(p
->frames
), gic(p
->gic
)
84 // Assert SPI ranges start at 32
85 for (int i
= 0; i
< frames
.size(); i
++) {
86 if (frames
[i
]->spi_base
< 32)
87 fatal("Gicv2m: Frame %d's SPI base (%d) is not in SPI space\n",
88 i
, frames
[i
]->spi_base
);
90 unsigned int x
= frames
.size();
91 fatal_if(!isPowerOf2(x
), "Gicv2m: The v2m shim must be configured with "
92 "a power-of-two number of frames\n");
93 log2framenum
= floorLog2(x
);
97 Gicv2m::getAddrRanges() const
100 for (int i
= 0; i
< frames
.size(); i
++) {
101 ranges
.push_back(RangeSize(frames
[i
]->addr
, FRAME_SIZE
));
107 Gicv2m::read(PacketPtr pkt
)
109 int frame
= frameFromAddr(pkt
->getAddr());
113 Addr offset
= pkt
->getAddr() - frames
[frame
]->addr
;
117 pkt
->set
<uint32_t>((frames
[frame
]->spi_base
<< 16) |
118 frames
[frame
]->spi_len
);
122 pkt
->set
<uint32_t>(0x4 | ((4+log2framenum
) << 4));
123 // Nr of 4KB blocks used by component. This is messy as frames are 64K
124 // (16, ie 2^4) and we should assert we're given a Po2 number of frames.
127 DPRINTF(GICV2M
, "GICv2m: Read of unk reg %#x\n", offset
);
128 pkt
->set
<uint32_t>(0);
131 pkt
->makeAtomicResponse();
137 Gicv2m::write(PacketPtr pkt
)
139 int frame
= frameFromAddr(pkt
->getAddr());
143 Addr offset
= pkt
->getAddr() - frames
[frame
]->addr
;
145 if (offset
== MSI_SETSPI_NSR
) {
146 /* Is payload SPI number within range? */
147 uint32_t m
= pkt
->get
<uint32_t>();
148 if (m
>= frames
[frame
]->spi_base
&&
149 m
< (frames
[frame
]->spi_base
+ frames
[frame
]->spi_len
)) {
150 DPRINTF(GICV2M
, "GICv2m: Frame %d raising MSI %d\n", frame
, m
);
154 DPRINTF(GICV2M
, "GICv2m: Write of unk reg %#x\n", offset
);
157 pkt
->makeAtomicResponse();
163 Gicv2m::frameFromAddr(Addr a
) const
165 for (int i
= 0; i
< frames
.size(); i
++) {
166 if (a
>= frames
[i
]->addr
&& a
< (frames
[i
]->addr
+ FRAME_SIZE
))