arch-arm, configs: Treat the bootloader rom as cacheable memory
[gem5.git] / src / dev / arm / gic_v2m.cc
1 /*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Matt Evans
38 */
39
40 /** @file
41 * Implementiation of a GICv2m MSI shim.
42 *
43 * This shim adds MSI support to GICv2.
44 *
45 * This should be instantiated with the appropriate number of frames,
46 * and SPI numbers thereof, to the system being modelled.
47 *
48 * For example, in RealView.py (or whichever board setup is used), instantiate:
49 *
50 * gicv2m = Gicv2m(frames=[
51 * Gicv2mFrame(addr=0x12340000, spi_base=320, spi_len=64),
52 * Gicv2mFrame(addr=0x12350000, spi_base=100, spi_len=32),
53 * Gicv2mFrame(addr=0x12360000, spi_base=150, spi_len=16),
54 * Gicv2mFrame(addr=0x12370000, spi_base=190, spi_len=8),
55 * ])
56 *
57 */
58
59 #include "dev/arm/gic_v2m.hh"
60
61 #include "base/bitunion.hh"
62 #include "base/intmath.hh"
63 #include "debug/Checkpoint.hh"
64 #include "debug/GICV2M.hh"
65 #include "dev/io_device.hh"
66 #include "mem/packet.hh"
67 #include "mem/packet_access.hh"
68
69 Gicv2m *
70 Gicv2mParams::create()
71 {
72 return new Gicv2m(this);
73 }
74
75 Gicv2mFrame *
76 Gicv2mFrameParams::create()
77 {
78 return new Gicv2mFrame(this);
79 }
80
81 Gicv2m::Gicv2m(const Params *p)
82 : PioDevice(p), pioDelay(p->pio_delay), frames(p->frames), gic(p->gic)
83 {
84 // Assert SPI ranges start at 32
85 for (int i = 0; i < frames.size(); i++) {
86 if (frames[i]->spi_base < 32)
87 fatal("Gicv2m: Frame %d's SPI base (%d) is not in SPI space\n",
88 i, frames[i]->spi_base);
89 }
90 unsigned int x = frames.size();
91 fatal_if(!isPowerOf2(x), "Gicv2m: The v2m shim must be configured with "
92 "a power-of-two number of frames\n");
93 log2framenum = floorLog2(x);
94 }
95
96 AddrRangeList
97 Gicv2m::getAddrRanges() const
98 {
99 AddrRangeList ranges;
100 for (int i = 0; i < frames.size(); i++) {
101 ranges.push_back(RangeSize(frames[i]->addr, FRAME_SIZE));
102 }
103 return ranges;
104 }
105
106 Tick
107 Gicv2m::read(PacketPtr pkt)
108 {
109 int frame = frameFromAddr(pkt->getAddr());
110
111 assert(frame >= 0);
112
113 Addr offset = pkt->getAddr() - frames[frame]->addr;
114
115 switch (offset) {
116 case MSI_TYPER:
117 pkt->set<uint32_t>((frames[frame]->spi_base << 16) |
118 frames[frame]->spi_len);
119 break;
120
121 case PER_ID4:
122 pkt->set<uint32_t>(0x4 | ((4+log2framenum) << 4));
123 // Nr of 4KB blocks used by component. This is messy as frames are 64K
124 // (16, ie 2^4) and we should assert we're given a Po2 number of frames.
125 break;
126 default:
127 DPRINTF(GICV2M, "GICv2m: Read of unk reg %#x\n", offset);
128 pkt->set<uint32_t>(0);
129 };
130
131 pkt->makeAtomicResponse();
132
133 return pioDelay;
134 }
135
136 Tick
137 Gicv2m::write(PacketPtr pkt)
138 {
139 int frame = frameFromAddr(pkt->getAddr());
140
141 assert(frame >= 0);
142
143 Addr offset = pkt->getAddr() - frames[frame]->addr;
144
145 if (offset == MSI_SETSPI_NSR) {
146 /* Is payload SPI number within range? */
147 uint32_t m = pkt->get<uint32_t>();
148 if (m >= frames[frame]->spi_base &&
149 m < (frames[frame]->spi_base + frames[frame]->spi_len)) {
150 DPRINTF(GICV2M, "GICv2m: Frame %d raising MSI %d\n", frame, m);
151 gic->sendInt(m);
152 }
153 } else {
154 DPRINTF(GICV2M, "GICv2m: Write of unk reg %#x\n", offset);
155 }
156
157 pkt->makeAtomicResponse();
158
159 return pioDelay;
160 }
161
162 int
163 Gicv2m::frameFromAddr(Addr a) const
164 {
165 for (int i = 0; i < frames.size(); i++) {
166 if (a >= frames[i]->addr && a < (frames[i]->addr + FRAME_SIZE))
167 return i;
168 }
169 return -1;
170 }