src/dev/arm/gic_v3.hh

   1 /*
   2  * Copyright (c) 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2018 Metempsy Technology Consulting
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __DEV_ARM_GICV3_H__
  42 #define __DEV_ARM_GICV3_H__
  43
  44 #include "dev/arm/base_gic.hh"
  45 #include "params/Gicv3.hh"
  46
  47 class Gicv3CPUInterface;
  48 class Gicv3Distributor;
  49 class Gicv3Redistributor;
  50 class Gicv3Its;
  51
  52 class Gicv3 : public BaseGic
  53 {
  54   protected:
  55     friend class Gicv3CPUInterface;
  56     friend class Gicv3Redistributor;
  57
  58     typedef Gicv3Params Params;
  59     Gicv3Distributor * distributor;
  60     std::vector<Gicv3Redistributor *> redistributors;
  61     std::vector<Gicv3CPUInterface *> cpuInterfaces;
  62     Gicv3Its * its;
  63     AddrRange distRange;
  64     AddrRange redistRange;
  65     AddrRangeList addrRanges;
  66     uint64_t redistSize;
  67
  68   public:
  69
  70     // Special interrupt IDs, as per SPEC 2.2.1 section
  71     static const int INTID_SECURE = 1020;
  72     static const int INTID_NONSECURE = 1021;
  73     static const int INTID_SPURIOUS = 1023;
  74
  75     // Number of Software Generated Interrupts
  76     static const int SGI_MAX = 16;
  77     // Number of Private Peripheral Interrupts
  78     static const int PPI_MAX = 16;
  79
  80     // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
  81     typedef enum {
  82         INT_INACTIVE,
  83         INT_PENDING,
  84         INT_ACTIVE,
  85         INT_ACTIVE_PENDING,
  86     } IntStatus;
  87
  88     // Interrupt groups, as per SPEC section 4.6
  89     typedef enum {
  90         G0S,
  91         G1S,
  92         G1NS,
  93     } GroupId;
  94
  95     typedef enum {
  96         INT_LEVEL_SENSITIVE,
  97         INT_EDGE_TRIGGERED,
  98     } IntTriggerType;
  99
 100   protected:
 101
 102     void clearInt(uint32_t int_id) override;
 103     void clearPPInt(uint32_t int_id, uint32_t cpu) override;
 104
 105     inline AddrRangeList
 106     getAddrRanges() const override
 107     {
 108         return addrRanges;
 109     }
 110
 111     void init() override;
 112
 113     const Params *
 114     params() const
 115     {
 116         return dynamic_cast<const Params *>(_params);
 117     }
 118
 119     Tick read(PacketPtr pkt) override;
 120     void reset();
 121     void sendInt(uint32_t int_id) override;
 122     void sendPPInt(uint32_t int_id, uint32_t cpu) override;
 123     void serialize(CheckpointOut & cp) const override;
 124     void unserialize(CheckpointIn & cp) override;
 125     Tick write(PacketPtr pkt) override;
 126     bool supportsVersion(GicVersion version) override;
 127
 128   public:
 129
 130     Gicv3(const Params * p);
 131     void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
 132
 133     inline Gicv3CPUInterface *
 134     getCPUInterface(int cpu_id) const
 135     {
 136         assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
 137         return cpuInterfaces[cpu_id];
 138     }
 139
 140     inline Gicv3Distributor *
 141     getDistributor() const
 142     {
 143         return distributor;
 144     }
 145
 146     inline Gicv3Redistributor *
 147     getRedistributor(ContextID context_id) const
 148     {
 149         assert(context_id < redistributors.size() and
 150                redistributors[context_id]);
 151         return redistributors[context_id];
 152     }
 153
 154     Gicv3Redistributor *
 155     getRedistributorByAffinity(uint32_t affinity) const;
 156
 157     Gicv3Redistributor *
 158     getRedistributorByAddr(Addr address) const;
 159
 160     void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
 161 };
 162
 163 #endif //__DEV_ARM_GICV3_H__