src/dev/arm/gic_v3_cpu_interface.hh

   1 /*
   2  * Copyright (c) 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2018 Metempsy Technology Consulting
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__
  42 #define __DEV_ARM_GICV3_CPU_INTERFACE_H__
  43
  44 #include "arch/arm/isa_device.hh"
  45 #include "dev/arm/gic_v3.hh"
  46
  47 class Gicv3Distributor;
  48 class Gicv3Redistributor;
  49
  50 class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
  51 {
  52   private:
  53
  54     friend class Gicv3Distributor;
  55     friend class Gicv3Redistributor;
  56
  57   protected:
  58
  59     Gicv3 * gic;
  60     Gicv3Redistributor * redistributor;
  61     Gicv3Distributor * distributor;
  62     uint32_t cpuId;
  63
  64     ArmInterruptPin *maintenanceInterrupt;
  65
  66     BitUnion64(ICC_CTLR_EL1)
  67         Bitfield<63, 20> res0_3;
  68         Bitfield<19>     ExtRange;
  69         Bitfield<18>     RSS;
  70         Bitfield<17, 16> res0_2;
  71         Bitfield<15>     A3V;
  72         Bitfield<14>     SEIS;
  73         Bitfield<13, 11> IDbits;
  74         Bitfield<10, 8>  PRIbits;
  75         Bitfield<7>      res0_1;
  76         Bitfield<6>      PMHE;
  77         Bitfield<5, 2>   res0_0;
  78         Bitfield<1>      EOImode;
  79         Bitfield<0>      CBPR;
  80     EndBitUnion(ICC_CTLR_EL1)
  81
  82     BitUnion64(ICC_CTLR_EL3)
  83         Bitfield<63, 20> res0_2;
  84         Bitfield<19>     ExtRange;
  85         Bitfield<18>     RSS;
  86         Bitfield<17>     nDS;
  87         Bitfield<16>     res0_1;
  88         Bitfield<15>     A3V;
  89         Bitfield<14>     SEIS;
  90         Bitfield<13, 11> IDbits;
  91         Bitfield<10, 8>  PRIbits;
  92         Bitfield<7>      res0_0;
  93         Bitfield<6>      PMHE;
  94         Bitfield<5>      RM;
  95         Bitfield<4>      EOImode_EL1NS;
  96         Bitfield<3>      EOImode_EL1S;
  97         Bitfield<2>      EOImode_EL3;
  98         Bitfield<1>      CBPR_EL1NS;
  99         Bitfield<0>      CBPR_EL1S;
 100     EndBitUnion(ICC_CTLR_EL3)
 101
 102     BitUnion64(ICC_IGRPEN0_EL1)
 103         Bitfield<63, 1> res0;
 104         Bitfield<0>     Enable;
 105     EndBitUnion(ICC_IGRPEN0_EL1)
 106
 107     BitUnion64(ICC_IGRPEN1_EL1)
 108         Bitfield<63, 1> res0;
 109         Bitfield<0>     Enable;
 110     EndBitUnion(ICC_IGRPEN1_EL1)
 111
 112     BitUnion64(ICC_IGRPEN1_EL3)
 113         Bitfield<63, 2> res0;
 114         Bitfield<1>     EnableGrp1S;
 115         Bitfield<0>     EnableGrp1NS;
 116     EndBitUnion(ICC_IGRPEN1_EL3)
 117
 118     BitUnion64(ICC_SRE_EL1)
 119         Bitfield<63, 3> res0;
 120         Bitfield<2>     DIB;
 121         Bitfield<1>     DFB;
 122         Bitfield<0>     SRE;
 123     EndBitUnion(ICC_SRE_EL1)
 124
 125     BitUnion64(ICC_SRE_EL2)
 126         Bitfield<63, 4> res0;
 127         Bitfield<3>     Enable;
 128         Bitfield<2>     DIB;
 129         Bitfield<1>     DFB;
 130         Bitfield<0>     SRE;
 131     EndBitUnion(ICC_SRE_EL2)
 132
 133     BitUnion64(ICC_SRE_EL3)
 134         Bitfield<63, 4> res0;
 135         Bitfield<3>     Enable;
 136         Bitfield<2>     DIB;
 137         Bitfield<1>     DFB;
 138         Bitfield<0>     SRE;
 139     EndBitUnion(ICC_SRE_EL3)
 140
 141     static const uint8_t PRIORITY_BITS = 5;
 142
 143     // Minimum BPR for Secure, or when security not enabled
 144     static const uint8_t GIC_MIN_BPR = 2;
 145     //  Minimum BPR for Nonsecure when security is enabled
 146     static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
 147
 148     static const uint8_t VIRTUAL_PRIORITY_BITS   = 5;
 149     static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
 150     static const uint8_t VIRTUAL_NUM_LIST_REGS   = 16;
 151
 152     static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
 153
 154     typedef struct {
 155         uint32_t intid;
 156         uint8_t prio;
 157         Gicv3::GroupId group;
 158     } hppi_t;
 159
 160     hppi_t hppi;
 161
 162     // GIC CPU interface memory mapped control registers (legacy)
 163     enum {
 164         GICC_CTLR    = 0x0000,
 165         GICC_PMR     = 0x0004,
 166         GICC_BPR     = 0x0008,
 167         GICC_IAR     = 0x000C,
 168         GICC_EOIR    = 0x0010,
 169         GICC_RPR     = 0x0014,
 170         GICC_HPPI    = 0x0018,
 171         GICC_ABPR    = 0x001C,
 172         GICC_AIAR    = 0x0020,
 173         GICC_AEOIR   = 0x0024,
 174         GICC_AHPPIR  = 0x0028,
 175         GICC_STATUSR = 0x002C,
 176         GICC_IIDR    = 0x00FC,
 177     };
 178
 179     static const AddrRange GICC_APR;
 180     static const AddrRange GICC_NSAPR;
 181
 182     // GIC CPU virtual interface memory mapped control registers (legacy)
 183     enum {
 184         GICH_HCR   = 0x0000,
 185         GICH_VTR   = 0x0004,
 186         GICH_VMCR  = 0x0008,
 187         GICH_MISR  = 0x0010,
 188         GICH_EISR  = 0x0020,
 189         GICH_ELRSR = 0x0030,
 190     };
 191
 192     static const AddrRange GICH_APR;
 193     static const AddrRange GICH_LR;
 194
 195     BitUnion64(ICH_HCR_EL2)
 196         Bitfield<63, 32> res0_2;
 197         Bitfield<31, 27> EOIcount;
 198         Bitfield<26, 15> res0_1;
 199         Bitfield<14>     TDIR;
 200         Bitfield<13>     TSEI;
 201         Bitfield<12>     TALL1;
 202         Bitfield<11>     TALL0;
 203         Bitfield<10>     TC;
 204         Bitfield<9, 8>   res0_0;
 205         Bitfield<7>      VGrp1DIE;
 206         Bitfield<6>      VGrp1EIE;
 207         Bitfield<5>      VGrp0DIE;
 208         Bitfield<4>      VGrp0EIE;
 209         Bitfield<3>      NPIE;
 210         Bitfield<2>      LRENPIE;
 211         Bitfield<1>      UIE;
 212         Bitfield<0>      En;
 213     EndBitUnion(ICH_HCR_EL2)
 214
 215     BitUnion64(ICH_LR_EL2)
 216         Bitfield<63, 62> State;
 217         Bitfield<61>     HW;
 218         Bitfield<60>     Group;
 219         Bitfield<59, 56> res0_1;
 220         Bitfield<55, 48> Priority;
 221         Bitfield<47, 45> res0_0;
 222         Bitfield<44, 32> pINTID;
 223         Bitfield<41>     EOI;
 224         Bitfield<31, 0>  vINTID;
 225     EndBitUnion(ICH_LR_EL2)
 226
 227     static const uint64_t ICH_LR_EL2_STATE_INVALID        = 0;
 228     static const uint64_t ICH_LR_EL2_STATE_PENDING        = 1;
 229     static const uint64_t ICH_LR_EL2_STATE_ACTIVE         = 2;
 230     static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
 231
 232     BitUnion32(ICH_LRC)
 233         Bitfield<31, 30> State;
 234         Bitfield<29>     HW;
 235         Bitfield<28>     Group;
 236         Bitfield<27, 24> res0_1;
 237         Bitfield<23, 16> Priority;
 238         Bitfield<15, 13> res0_0;
 239         Bitfield<12, 0>  pINTID;
 240         Bitfield<9>      EOI;
 241     EndBitUnion(ICH_LRC)
 242
 243     BitUnion64(ICH_MISR_EL2)
 244         Bitfield<63, 8> res0;
 245         Bitfield<7>     VGrp1D;
 246         Bitfield<6>     VGrp1E;
 247         Bitfield<5>     VGrp0D;
 248         Bitfield<4>     VGrp0E;
 249         Bitfield<3>     NP;
 250         Bitfield<2>     LRENP;
 251         Bitfield<1>     U;
 252         Bitfield<0>     EOI;
 253     EndBitUnion(ICH_MISR_EL2)
 254
 255     BitUnion64(ICH_VMCR_EL2)
 256         Bitfield<63, 32> res0_2;
 257         Bitfield<31, 24> VPMR;
 258         Bitfield<23, 21> VBPR0;
 259         Bitfield<20, 18> VBPR1;
 260         Bitfield<17, 10> res0_1;
 261         Bitfield<9>      VEOIM;
 262         Bitfield<8, 5>   res0_0;
 263         Bitfield<4>      VCBPR;
 264         Bitfield<3>      VFIQEn;
 265         Bitfield<2>      VAckCtl;
 266         Bitfield<1>      VENG1;
 267         Bitfield<0>      VENG0;
 268     EndBitUnion(ICH_VMCR_EL2)
 269
 270     BitUnion64(ICH_VTR_EL2)
 271         Bitfield<63, 32> res0_1;
 272         Bitfield<31, 29> PRIbits;
 273         Bitfield<28, 26> PREbits;
 274         Bitfield<25, 23> IDbits;
 275         Bitfield<22>     SEIS;
 276         Bitfield<21>     A3V;
 277         Bitfield<20>     res1;
 278         Bitfield<19>     TDS;
 279         Bitfield<18, 5>  res0_0;
 280         Bitfield<4, 0>   ListRegs;
 281     EndBitUnion(ICH_VTR_EL2)
 282
 283     BitUnion64(ICV_CTLR_EL1)
 284         Bitfield<63, 19> res0_2;
 285         Bitfield<18>     RSS;
 286         Bitfield<17, 16> res0_1;
 287         Bitfield<15>     A3V;
 288         Bitfield<14>     SEIS;
 289         Bitfield<13, 11> IDbits;
 290         Bitfield<10, 8>  PRIbits;
 291         Bitfield<7, 2>   res0_0;
 292         Bitfield<1>      EOImode;
 293         Bitfield<0>      CBPR;
 294     EndBitUnion(ICV_CTLR_EL1)
 295
 296   protected:
 297
 298     void activateIRQ(uint32_t intid, Gicv3::GroupId group);
 299     void generateSGI(RegVal val, Gicv3::GroupId group);
 300     int currEL() const;
 301     void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
 302     void dropPriority(Gicv3::GroupId group);
 303     uint64_t eoiMaintenanceInterruptStatus() const;
 304     bool getHCREL2FMO() const;
 305     bool getHCREL2IMO() const;
 306     uint32_t getHPPIR0() const;
 307     uint32_t getHPPIR1() const;
 308     int getHPPVILR() const;
 309     bool groupEnabled(Gicv3::GroupId group) const;
 310     uint32_t groupPriorityMask(Gicv3::GroupId group);
 311     bool haveEL(ArmISA::ExceptionLevel el) const;
 312     int highestActiveGroup() const;
 313     uint8_t highestActivePriority() const;
 314     bool hppiCanPreempt();
 315     bool hppviCanPreempt(int lrIdx) const;
 316     bool inSecureState() const;
 317     ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
 318     bool isAA64() const;
 319     bool isEL3OrMon() const;
 320     bool isEOISplitMode() const;
 321     bool isSecureBelowEL3() const;
 322     ICH_MISR_EL2 maintenanceInterruptStatus() const;
 323     void resetHppi(uint32_t intid);
 324     void serialize(CheckpointOut & cp) const override;
 325     void unserialize(CheckpointIn & cp) override;
 326     void update();
 327     void updateDistributor();
 328     void virtualActivateIRQ(uint32_t lrIdx);
 329     void virtualDeactivateIRQ(int lrIdx);
 330     uint8_t virtualDropPriority();
 331     int virtualFindActive(uint32_t intid) const;
 332     uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
 333     uint8_t virtualHighestActivePriority() const;
 334     void virtualIncrementEOICount();
 335     bool virtualIsEOISplitMode() const;
 336     void virtualUpdate();
 337     RegVal bpr1(Gicv3::GroupId group);
 338     bool havePendingInterrupts(void) const;
 339     void clearPendingInterrupts(void);
 340     void assertWakeRequest(void);
 341     void deassertWakeRequest(void);
 342
 343     RegVal readBankedMiscReg(MiscRegIndex misc_reg) const;
 344     void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
 345   public:
 346
 347     Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
 348
 349     void init();
 350
 351   public: // BaseISADevice
 352     RegVal readMiscReg(int misc_reg) override;
 353     void setMiscReg(int misc_reg, RegVal val) override;
 354     void setThreadContext(ThreadContext *tc) override;
 355 };
 356
 357 #endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__