src/dev/arm/gic_v3_redistributor.hh

   1 /*
   2  * Copyright (c) 2018 Metempsy Technology Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Jairo Balart
  29  */
  30
  31 #ifndef __DEV_ARM_GICV3_REDISTRIBUTOR_H__
  32 #define __DEV_ARM_GICV3_REDISTRIBUTOR_H__
  33
  34 #include "base/addr_range.hh"
  35 #include "dev/arm/gic_v3.hh"
  36 #include "sim/serialize.hh"
  37
  38 class Gicv3Distributor;
  39 class Gicv3CPUInterface;
  40
  41 class Gicv3Redistributor : public Serializable
  42 {
  43   private:
  44
  45     friend class Gicv3CPUInterface;
  46     friend class Gicv3Distributor;
  47
  48   protected:
  49
  50     Gicv3 * gic;
  51     Gicv3Distributor * distributor;
  52     Gicv3CPUInterface * cpuInterface;
  53     uint32_t cpuId;
  54
  55     /*
  56      * GICv3 defines 2 contiguous 64KB frames for each redistributor.
  57      * Order of frames must be RD_base, SGI_base.
  58      */
  59     static const uint32_t RD_base = 0x0;
  60     static const uint32_t SGI_base = 0x10000;
  61
  62     enum {
  63         // Control Register
  64         GICR_CTLR  = RD_base + 0x0000,
  65         // Implementer Identification Register
  66         GICR_IIDR = RD_base + 0x0004,
  67         // Type Register
  68         GICR_TYPER = RD_base + 0x0008,
  69         // Wake Register
  70         GICR_WAKER = RD_base + 0x0014,
  71         // Peripheral ID0 Register
  72         GICR_PIDR0 = RD_base + 0xffe0,
  73         // Peripheral ID1 Register
  74         GICR_PIDR1 = RD_base + 0xffe4,
  75         // Peripheral ID2 Register
  76         GICR_PIDR2 = RD_base + 0xffe8,
  77         // Peripheral ID3 Register
  78         GICR_PIDR3 = RD_base + 0xffec,
  79         // Peripheral ID4 Register
  80         GICR_PIDR4 = RD_base + 0xffd0,
  81         // Peripheral ID5 Register
  82         GICR_PIDR5 = RD_base + 0xffd4,
  83         // Peripheral ID6 Register
  84         GICR_PIDR6 = RD_base + 0xffd8,
  85         // Peripheral ID7 Register
  86         GICR_PIDR7 = RD_base + 0xffdc,
  87     };
  88
  89     static const uint32_t GICR_WAKER_ProcessorSleep = 1 << 1;
  90     static const uint32_t GICR_WAKER_ChildrenAsleep = 1 << 2;
  91
  92     bool peInLowPowerState;
  93
  94     enum {
  95         // Interrupt Group Register 0
  96         GICR_IGROUPR0   = SGI_base + 0x0080,
  97         // Interrupt Set-Enable Register 0
  98         GICR_ISENABLER0 = SGI_base + 0x0100,
  99         // Interrupt Clear-Enable Register 0
 100         GICR_ICENABLER0 = SGI_base + 0x0180,
 101         // Interrupt Set-Pending Register 0
 102         GICR_ISPENDR0 = SGI_base + 0x0200,
 103         // Interrupt Clear-Pending Register 0
 104         GICR_ICPENDR0 = SGI_base + 0x0280,
 105         // Interrupt Set-Active Register 0
 106         GICR_ISACTIVER0 = SGI_base + 0x0300,
 107         // Interrupt Clear-Active Register 0
 108         GICR_ICACTIVER0 = SGI_base + 0x0380,
 109         // SGI Configuration Register
 110         GICR_ICFGR0 = SGI_base + 0x0c00,
 111         // PPI Configuration Register
 112         GICR_ICFGR1 = SGI_base + 0x0c04,
 113         // Interrupt Group Modifier Register 0
 114         GICR_IGRPMODR0 = SGI_base + 0x0d00,
 115         // Non-secure Access Control Register
 116         GICR_NSACR = SGI_base + 0x0e00,
 117     };
 118
 119     // Interrupt Priority Registers
 120     static const AddrRange GICR_IPRIORITYR;
 121
 122     std::vector <uint8_t> irqGroup;
 123     std::vector <bool> irqEnabled;
 124     std::vector <bool> irqPending;
 125     std::vector <bool> irqActive;
 126     std::vector <uint8_t> irqPriority;
 127     std::vector <Gicv3::IntTriggerType> irqConfig;
 128     std::vector <uint8_t> irqGrpmod;
 129     std::vector <uint8_t> irqNsacr;
 130
 131     bool DPG1S;
 132     bool DPG1NS;
 133     bool DPG0;
 134
 135     static const uint32_t GICR_CTLR_DPG0 = 1 << 24;
 136     static const uint32_t GICR_CTLR_DPG1NS = 1 << 25;
 137     static const uint32_t GICR_CTLR_DPG1S = 1 << 26;
 138
 139   public:
 140
 141     /*
 142      * GICv3 defines only 2 64K consecutive frames for the redistributor
 143      * (RD_base and SGI_base) but we are using 2 extra 64K stride frames
 144      * to match GICv4 that defines 4 64K consecutive frames for them.
 145      * Note this must match with DTB/DTS GIC node definition and boot
 146      * loader code.
 147      */
 148     static const uint32_t ADDR_RANGE_SIZE = 0x40000;
 149
 150     Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
 151     ~Gicv3Redistributor();
 152     void init();
 153     void initState();
 154
 155     uint64_t read(Addr addr, size_t size, bool is_secure_access);
 156     void write(Addr addr, uint64_t data, size_t size,
 157                bool is_secure_access);
 158     void sendPPInt(uint32_t int_id);
 159     void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
 160     void serialize(CheckpointOut & cp) const override;
 161     void unserialize(CheckpointIn & cp) override;
 162     uint32_t getAffinity();
 163
 164     Gicv3CPUInterface *
 165     getCPUInterface() const
 166     {
 167         return cpuInterface;
 168     }
 169
 170     bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group);
 171
 172   protected:
 173
 174     void reset();
 175     void update();
 176     void updateAndInformCPUInterface();
 177     Gicv3::IntStatus intStatus(uint32_t int_id);
 178     Gicv3::GroupId getIntGroup(int int_id);
 179     void activateIRQ(uint32_t int_id);
 180     void deactivateIRQ(uint32_t int_id);
 181 };
 182
 183 #endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__