src/dev/arm/kmi.cc

   1 /*
   2  * Copyright (c) 2010, 2017-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "dev/arm/kmi.hh"
  42
  43 #include "base/trace.hh"
  44 #include "base/vnc/vncinput.hh"
  45 #include "debug/Pl050.hh"
  46 #include "dev/arm/amba_device.hh"
  47 #include "dev/ps2/device.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/packet_access.hh"
  50
  51 Pl050::Pl050(const Pl050Params *p)
  52     : AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
  53       rawInterrupts(0),
  54       ps2(p->ps2)
  55 {
  56     ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
  57 }
  58
  59 Tick
  60 Pl050::read(PacketPtr pkt)
  61 {
  62     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  63
  64     Addr daddr = pkt->getAddr() - pioAddr;
  65
  66     uint32_t data = 0;
  67
  68     switch (daddr) {
  69       case kmiCr:
  70         DPRINTF(Pl050, "Read Commmand: %#x\n", (uint32_t)control);
  71         data = control;
  72         break;
  73
  74       case kmiStat:
  75         status.rxfull = ps2->hostDataAvailable() ? 1 : 0;
  76         DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status);
  77         data = status;
  78         break;
  79
  80       case kmiData:
  81         data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
  82         updateRxInt();
  83         DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
  84         break;
  85
  86       case kmiClkDiv:
  87         data = clkdiv;
  88         break;
  89
  90       case kmiISR:
  91         data = getInterrupt();
  92         DPRINTF(Pl050, "Read Interrupts: %#x\n", getInterrupt());
  93         break;
  94
  95       default:
  96         if (readId(pkt, ambaId, pioAddr)) {
  97             // Hack for variable size accesses
  98             data = pkt->getUintX(LittleEndianByteOrder);
  99             break;
 100         }
 101
 102         warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr);
 103         break;
 104     }
 105
 106     pkt->setUintX(data, LittleEndianByteOrder);
 107     pkt->makeAtomicResponse();
 108     return pioDelay;
 109 }
 110
 111 Tick
 112 Pl050::write(PacketPtr pkt)
 113 {
 114
 115     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 116
 117     Addr daddr = pkt->getAddr() - pioAddr;
 118     const uint32_t data = pkt->getUintX(LittleEndianByteOrder);
 119
 120     panic_if(pkt->getSize() != 1,
 121              "PL050: Unexpected write size "
 122              "(offset: %#x, data: %#x, size: %u)\n",
 123              daddr, data, pkt->getSize());
 124
 125     switch (daddr) {
 126       case kmiCr:
 127         DPRINTF(Pl050, "Write Commmand: %#x\n", data);
 128         // Use the update interrupts helper to make sure any interrupt
 129         // mask changes are handled correctly.
 130         setControl((uint8_t)data);
 131         break;
 132
 133       case kmiData:
 134         DPRINTF(Pl050, "Write Data: %#x\n", data);
 135         // Clear the TX interrupt before writing new data.
 136         setTxInt(false);
 137         ps2->hostWrite((uint8_t)data);
 138         // Data is written in 0 time, so raise the TX interrupt again.
 139         setTxInt(true);
 140         break;
 141
 142       case kmiClkDiv:
 143         clkdiv = (uint8_t)data;
 144         break;
 145
 146       default:
 147         warn("PL050: Unhandled write of %#x to offset %#x\n", data, daddr);
 148         break;
 149     }
 150
 151     pkt->makeAtomicResponse();
 152     return pioDelay;
 153 }
 154
 155 void
 156 Pl050::setTxInt(bool value)
 157 {
 158     InterruptReg ints = rawInterrupts;
 159
 160     ints.tx = value ? 1 : 0;
 161
 162     setInterrupts(ints);
 163 }
 164
 165 void
 166 Pl050::updateRxInt()
 167 {
 168     InterruptReg ints = rawInterrupts;
 169
 170     ints.rx = ps2->hostDataAvailable() ? 1 : 0;
 171
 172     setInterrupts(ints);
 173 }
 174
 175 void
 176 Pl050::updateIntCtrl(InterruptReg ints, ControlReg ctrl)
 177 {
 178     const bool old_pending(getInterrupt());
 179     control = ctrl;
 180     rawInterrupts = ints;
 181     const bool new_pending(getInterrupt());
 182
 183     if (!old_pending && new_pending) {
 184         DPRINTF(Pl050, "Generate interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
 185                 rawInterrupts, control, getInterrupt());
 186         interrupt->raise();
 187     } else if (old_pending && !new_pending) {
 188         DPRINTF(Pl050, "Clear interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
 189                 rawInterrupts, control, getInterrupt());
 190         interrupt->clear();
 191     }
 192 }
 193
 194 Pl050::InterruptReg
 195 Pl050::getInterrupt() const
 196 {
 197     InterruptReg tmp_interrupt(0);
 198
 199     tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable;
 200     tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable;
 201
 202     return tmp_interrupt;
 203 }
 204
 205 void
 206 Pl050::serialize(CheckpointOut &cp) const
 207 {
 208     paramOut(cp, "ctrlreg", control);
 209     paramOut(cp, "stsreg", status);
 210     SERIALIZE_SCALAR(clkdiv);
 211     paramOut(cp, "raw_ints", rawInterrupts);
 212 }
 213
 214 void
 215 Pl050::unserialize(CheckpointIn &cp)
 216 {
 217     paramIn(cp, "ctrlreg", control);
 218     paramIn(cp, "stsreg", status);
 219     UNSERIALIZE_SCALAR(clkdiv);
 220     paramIn(cp, "raw_ints", rawInterrupts);
 221 }
 222
 223 Pl050 *
 224 Pl050Params::create()
 225 {
 226     return new Pl050(this);
 227 }