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44 #include "dev/arm/kmi.hh"
46 #include "base/trace.hh"
47 #include "base/vnc/vncinput.hh"
48 #include "debug/Pl050.hh"
49 #include "dev/arm/amba_device.hh"
50 #include "dev/ps2/device.hh"
51 #include "mem/packet.hh"
52 #include "mem/packet_access.hh"
54 Pl050::Pl050(const Pl050Params
*p
)
55 : AmbaIntDevice(p
, 0x1000), control(0), status(0x43), clkdiv(0),
59 ps2
->hostRegDataAvailable([this]() { this->updateRxInt(); });
63 Pl050::read(PacketPtr pkt
)
65 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
67 Addr daddr
= pkt
->getAddr() - pioAddr
;
73 DPRINTF(Pl050
, "Read Commmand: %#x\n", (uint32_t)control
);
78 status
.rxfull
= ps2
->hostDataAvailable() ? 1 : 0;
79 DPRINTF(Pl050
, "Read Status: %#x\n", (uint32_t)status
);
84 data
= ps2
->hostDataAvailable() ? ps2
->hostRead() : 0;
86 DPRINTF(Pl050
, "Read Data: %#x\n", (uint32_t)data
);
94 data
= getInterrupt();
95 DPRINTF(Pl050
, "Read Interrupts: %#x\n", getInterrupt());
99 if (readId(pkt
, ambaId
, pioAddr
)) {
100 // Hack for variable size accesses
101 data
= pkt
->getLE
<uint32_t>();
105 warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr
);
109 pkt
->setUintX(data
, LittleEndianByteOrder
);
110 pkt
->makeAtomicResponse();
115 Pl050::write(PacketPtr pkt
)
118 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
120 Addr daddr
= pkt
->getAddr() - pioAddr
;
121 const uint32_t data
= pkt
->getUintX(LittleEndianByteOrder
);
123 panic_if(pkt
->getSize() != 1,
124 "PL050: Unexpected write size "
125 "(offset: %#x, data: %#x, size: %u)\n",
126 daddr
, data
, pkt
->getSize());
130 DPRINTF(Pl050
, "Write Commmand: %#x\n", data
);
131 // Use the update interrupts helper to make sure any interrupt
132 // mask changes are handled correctly.
133 setControl((uint8_t)data
);
137 DPRINTF(Pl050
, "Write Data: %#x\n", data
);
138 // Clear the TX interrupt before writing new data.
140 ps2
->hostWrite((uint8_t)data
);
141 // Data is written in 0 time, so raise the TX interrupt again.
146 clkdiv
= (uint8_t)data
;
150 warn("PL050: Unhandled write of %#x to offset %#x\n", data
, daddr
);
154 pkt
->makeAtomicResponse();
159 Pl050::setTxInt(bool value
)
161 InterruptReg ints
= rawInterrupts
;
163 ints
.tx
= value
? 1 : 0;
171 InterruptReg ints
= rawInterrupts
;
173 ints
.rx
= ps2
->hostDataAvailable() ? 1 : 0;
179 Pl050::updateIntCtrl(InterruptReg ints
, ControlReg ctrl
)
181 const bool old_pending(getInterrupt());
183 rawInterrupts
= ints
;
184 const bool new_pending(getInterrupt());
186 if (!old_pending
&& new_pending
) {
187 DPRINTF(Pl050
, "Generate interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
188 rawInterrupts
, control
, getInterrupt());
189 gic
->sendInt(intNum
);
190 } else if (old_pending
&& !new_pending
) {
191 DPRINTF(Pl050
, "Clear interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
192 rawInterrupts
, control
, getInterrupt());
193 gic
->clearInt(intNum
);
198 Pl050::getInterrupt() const
200 InterruptReg
tmp_interrupt(0);
202 tmp_interrupt
.tx
= rawInterrupts
.tx
& control
.txint_enable
;
203 tmp_interrupt
.rx
= rawInterrupts
.rx
& control
.rxint_enable
;
205 return tmp_interrupt
;
209 Pl050::serialize(CheckpointOut
&cp
) const
211 paramOut(cp
, "ctrlreg", control
);
212 paramOut(cp
, "stsreg", status
);
213 SERIALIZE_SCALAR(clkdiv
);
214 paramOut(cp
, "raw_ints", rawInterrupts
);
218 Pl050::unserialize(CheckpointIn
&cp
)
220 paramIn(cp
, "ctrlreg", control
);
221 paramIn(cp
, "stsreg", status
);
222 UNSERIALIZE_SCALAR(clkdiv
);
223 paramIn(cp
, "raw_ints", rawInterrupts
);
227 Pl050Params::create()
229 return new Pl050(this);