2e80045e4f32f934ee46755214dd305f15c1a863
2 * Copyright (c) 2010, 2015 ARM Limited
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14 * Copyright (c) 2005 The Regents of The University of Michigan
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44 #include "dev/arm/pl011.hh"
46 #include "base/trace.hh"
47 #include "debug/Checkpoint.hh"
48 #include "debug/Uart.hh"
49 #include "dev/arm/amba_device.hh"
50 #include "dev/arm/base_gic.hh"
51 #include "mem/packet.hh"
52 #include "mem/packet_access.hh"
53 #include "params/Pl011.hh"
54 #include "sim/sim_exit.hh"
56 Pl011::Pl011(const Pl011Params
*p
)
58 intEvent([this]{ generateInterrupt(); }, name()),
59 control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
61 gic(p
->gic
), endOnEOT(p
->end_on_eot
), intNum(p
->int_num
),
62 intDelay(p
->int_delay
)
67 Pl011::read(PacketPtr pkt
)
69 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
71 Addr daddr
= pkt
->getAddr() - pioAddr
;
73 DPRINTF(Uart
, " read register %#x size=%d\n", daddr
, pkt
->getSize());
75 // use a temporary data since the uart registers are read/written with
76 // different size operations
83 if (device
->dataAvailable()) {
84 data
= device
->readData();
85 // Since we don't simulate a FIFO for incoming data, we
86 // assume it's empty and clear RXINTR and RTINTR.
87 clearInterrupts(UART_RXINTR
| UART_RTINTR
);
88 if (device
->dataAvailable()) {
89 DPRINTF(Uart
, "Re-raising interrupt due to more data "
90 "after UART_DR read\n");
96 data
= 0x0; // We never have errors
100 UART_FR_CTS
| // Clear To Send
101 // Given we do not simulate a FIFO we are either empty or full.
102 (!device
->dataAvailable() ? UART_FR_RXFE
: UART_FR_RXFF
) |
103 UART_FR_TXFE
; // TX FIFO empty
106 "Reading FR register as %#x rawInt=0x%x "
107 "imsc=0x%x maskInt=0x%x\n",
108 data
, rawInt
, imsc
, maskInt());
130 DPRINTF(Uart
, "Reading Raw Int status as 0x%x\n", rawInt
);
133 DPRINTF(Uart
, "Reading Masked Int status as 0x%x\n", maskInt());
137 warn("PL011: DMA not supported\n");
138 data
= 0x0; // DMA never enabled
141 if (readId(pkt
, AMBA_ID
, pioAddr
)) {
142 // Hack for variable size accesses
143 data
= pkt
->getLE
<uint32_t>();
147 panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr
);
151 switch(pkt
->getSize()) {
153 pkt
->setLE
<uint8_t>(data
);
156 pkt
->setLE
<uint16_t>(data
);
159 pkt
->setLE
<uint32_t>(data
);
162 panic("Uart read size too big?\n");
167 pkt
->makeAtomicResponse();
172 Pl011::write(PacketPtr pkt
)
175 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
177 Addr daddr
= pkt
->getAddr() - pioAddr
;
179 DPRINTF(Uart
, " write register %#x value %#x size=%d\n", daddr
,
180 pkt
->getLE
<uint8_t>(), pkt
->getSize());
182 // use a temporary data since the uart registers are read/written with
183 // different size operations
187 switch(pkt
->getSize()) {
189 data
= pkt
->getLE
<uint8_t>();
192 data
= pkt
->getLE
<uint16_t>();
195 data
= pkt
->getLE
<uint32_t>();
198 panic("Uart write size too big?\n");
205 if ((data
& 0xFF) == 0x04 && endOnEOT
)
206 exitSimLoop("UART received EOT", 0);
208 device
->writeData(data
& 0xFF);
209 // We're supposed to clear TXINTR when this register is
210 // written to, however. since we're also infinitely fast, we
211 // need to immediately raise it again.
212 clearInterrupts(UART_TXINTR
);
213 raiseInterrupts(UART_TXINTR
);
215 case UART_ECR
: // clears errors, ignore
233 DPRINTF(Uart
, "Setting interrupt mask 0x%x\n", data
);
234 setInterruptMask(data
);
238 DPRINTF(Uart
, "Clearing interrupts 0x%x\n", data
);
239 clearInterrupts(data
);
240 if (device
->dataAvailable()) {
241 DPRINTF(Uart
, "Re-raising interrupt due to more data after "
247 // DMA is not supported, so panic if anyome tries to enable it.
248 // Bits 0, 1, 2 enables DMA on RX, TX, ERR respectively, others res0.
250 panic("Tried to enable DMA on PL011\n");
252 warn("PL011: DMA not supported\n");
255 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr
);
258 pkt
->makeAtomicResponse();
263 Pl011::dataAvailable()
265 /*@todo ignore the fifo, just say we have data now
266 * We might want to fix this, or we might not care */
267 DPRINTF(Uart
, "Data available, scheduling interrupt\n");
268 raiseInterrupts(UART_RXINTR
| UART_RTINTR
);
272 Pl011::generateInterrupt()
274 DPRINTF(Uart
, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
275 imsc
, rawInt
, maskInt());
278 gic
->sendInt(intNum
);
279 DPRINTF(Uart
, " -- Generated\n");
284 Pl011::setInterrupts(uint16_t ints
, uint16_t mask
)
286 const bool old_ints(!!maskInt());
291 if (!old_ints
&& maskInt()) {
292 if (!intEvent
.scheduled())
293 schedule(intEvent
, curTick() + intDelay
);
294 } else if (old_ints
&& !maskInt()) {
295 gic
->clearInt(intNum
);
302 Pl011::serialize(CheckpointOut
&cp
) const
304 DPRINTF(Checkpoint
, "Serializing Arm PL011\n");
305 SERIALIZE_SCALAR(control
);
306 SERIALIZE_SCALAR(fbrd
);
307 SERIALIZE_SCALAR(ibrd
);
308 SERIALIZE_SCALAR(lcrh
);
309 SERIALIZE_SCALAR(ifls
);
311 // Preserve backwards compatibility by giving these silly names.
312 paramOut(cp
, "imsc_serial", imsc
);
313 paramOut(cp
, "rawInt_serial", rawInt
);
317 Pl011::unserialize(CheckpointIn
&cp
)
319 DPRINTF(Checkpoint
, "Unserializing Arm PL011\n");
321 UNSERIALIZE_SCALAR(control
);
322 UNSERIALIZE_SCALAR(fbrd
);
323 UNSERIALIZE_SCALAR(ibrd
);
324 UNSERIALIZE_SCALAR(lcrh
);
325 UNSERIALIZE_SCALAR(ifls
);
327 // Preserve backwards compatibility by giving these silly names.
328 paramIn(cp
, "imsc_serial", imsc
);
329 paramIn(cp
, "rawInt_serial", rawInt
);
333 Pl011Params::create()
335 return new Pl011(this);