src/dev/arm/pl011.cc

   1 /*
   2  * Copyright (c) 2010, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "dev/arm/pl011.hh"
  42
  43 #include "base/trace.hh"
  44 #include "debug/Checkpoint.hh"
  45 #include "debug/Uart.hh"
  46 #include "dev/arm/amba_device.hh"
  47 #include "dev/arm/base_gic.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/packet_access.hh"
  50 #include "params/Pl011.hh"
  51 #include "sim/sim_exit.hh"
  52
  53 Pl011::Pl011(const Pl011Params *p)
  54     : Uart(p, 0x1000),
  55       intEvent([this]{ generateInterrupt(); }, name()),
  56       control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
  57       imsc(0), rawInt(0),
  58       endOnEOT(p->end_on_eot), interrupt(p->interrupt->get()),
  59       intDelay(p->int_delay)
  60 {
  61 }
  62
  63 Tick
  64 Pl011::read(PacketPtr pkt)
  65 {
  66     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  67
  68     Addr daddr = pkt->getAddr() - pioAddr;
  69
  70     DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
  71
  72     // use a temporary data since the uart registers are read/written with
  73     // different size operations
  74     //
  75     uint32_t data = 0;
  76
  77     switch(daddr) {
  78       case UART_DR:
  79         data = 0;
  80         if (device->dataAvailable()) {
  81             data = device->readData();
  82             // Since we don't simulate a FIFO for incoming data, we
  83             // assume it's empty and clear RXINTR and RTINTR.
  84             clearInterrupts(UART_RXINTR | UART_RTINTR);
  85             if (device->dataAvailable()) {
  86                 DPRINTF(Uart, "Re-raising interrupt due to more data "
  87                         "after UART_DR read\n");
  88                 dataAvailable();
  89             }
  90         }
  91         break;
  92       case UART_RSR:
  93         data = 0x0; // We never have errors
  94         break;
  95       case UART_FR:
  96         data =
  97             UART_FR_CTS | // Clear To Send
  98             // Given we do not simulate a FIFO we are either empty or full.
  99             (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
 100             UART_FR_TXFE; // TX FIFO empty
 101
 102         DPRINTF(Uart,
 103                 "Reading FR register as %#x rawInt=0x%x "
 104                 "imsc=0x%x maskInt=0x%x\n",
 105                 data, rawInt, imsc, maskInt());
 106         break;
 107       case UART_CR:
 108         data = control;
 109         break;
 110       case UART_IBRD:
 111         data = ibrd;
 112         break;
 113       case UART_FBRD:
 114         data = fbrd;
 115         break;
 116       case UART_LCRH:
 117         data = lcrh;
 118         break;
 119       case UART_IFLS:
 120         data = ifls;
 121         break;
 122       case UART_IMSC:
 123         data = imsc;
 124         break;
 125       case UART_RIS:
 126         data = rawInt;
 127         DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
 128         break;
 129       case UART_MIS:
 130         DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
 131         data = maskInt();
 132         break;
 133       case UART_DMACR:
 134         warn("PL011: DMA not supported\n");
 135         data = 0x0; // DMA never enabled
 136         break;
 137       default:
 138         if (readId(pkt, AMBA_ID, pioAddr)) {
 139             // Hack for variable size accesses
 140             data = pkt->getUintX(LittleEndianByteOrder);
 141             break;
 142         }
 143
 144         panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
 145         break;
 146     }
 147
 148     switch(pkt->getSize()) {
 149       case 1:
 150         pkt->setLE<uint8_t>(data);
 151         break;
 152       case 2:
 153         pkt->setLE<uint16_t>(data);
 154         break;
 155       case 4:
 156         pkt->setLE<uint32_t>(data);
 157         break;
 158       default:
 159         panic("Uart read size too big?\n");
 160         break;
 161     }
 162
 163
 164     pkt->makeAtomicResponse();
 165     return pioDelay;
 166 }
 167
 168 Tick
 169 Pl011::write(PacketPtr pkt)
 170 {
 171
 172     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 173
 174     Addr daddr = pkt->getAddr() - pioAddr;
 175
 176     DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
 177             pkt->getLE<uint8_t>(), pkt->getSize());
 178
 179     // use a temporary data since the uart registers are read/written with
 180     // different size operations
 181     //
 182     uint32_t data = 0;
 183
 184     switch(pkt->getSize()) {
 185       case 1:
 186         data = pkt->getLE<uint8_t>();
 187         break;
 188       case 2:
 189         data = pkt->getLE<uint16_t>();
 190         break;
 191       case 4:
 192         data = pkt->getLE<uint32_t>();
 193         break;
 194       default:
 195         panic("Uart write size too big?\n");
 196         break;
 197     }
 198
 199
 200     switch (daddr) {
 201         case UART_DR:
 202           if ((data & 0xFF) == 0x04 && endOnEOT)
 203             exitSimLoop("UART received EOT", 0);
 204
 205         device->writeData(data & 0xFF);
 206         // We're supposed to clear TXINTR when this register is
 207         // written to, however. since we're also infinitely fast, we
 208         // need to immediately raise it again.
 209         clearInterrupts(UART_TXINTR);
 210         raiseInterrupts(UART_TXINTR);
 211         break;
 212       case UART_ECR: // clears errors, ignore
 213         break;
 214       case UART_CR:
 215         control = data;
 216         break;
 217       case UART_IBRD:
 218         ibrd = data;
 219         break;
 220       case UART_FBRD:
 221         fbrd = data;
 222         break;
 223       case UART_LCRH:
 224         lcrh = data;
 225         break;
 226       case UART_IFLS:
 227         ifls = data;
 228         break;
 229       case UART_IMSC:
 230         DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
 231         setInterruptMask(data);
 232         break;
 233
 234       case UART_ICR:
 235         DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
 236         clearInterrupts(data);
 237         if (device->dataAvailable()) {
 238             DPRINTF(Uart, "Re-raising interrupt due to more data after "
 239                     "UART_ICR write\n");
 240             dataAvailable();
 241         }
 242         break;
 243       case UART_DMACR:
 244         // DMA is not supported, so panic if anyome tries to enable it.
 245         // Bits 0, 1, 2 enables DMA on RX, TX, ERR respectively, others res0.
 246         if (data & 0x7) {
 247             panic("Tried to enable DMA on PL011\n");
 248         }
 249         warn("PL011: DMA not supported\n");
 250         break;
 251       default:
 252         panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
 253         break;
 254     }
 255     pkt->makeAtomicResponse();
 256     return pioDelay;
 257 }
 258
 259 void
 260 Pl011::dataAvailable()
 261 {
 262     /*@todo ignore the fifo, just say we have data now
 263      * We might want to fix this, or we might not care */
 264     DPRINTF(Uart, "Data available, scheduling interrupt\n");
 265     raiseInterrupts(UART_RXINTR | UART_RTINTR);
 266 }
 267
 268 void
 269 Pl011::generateInterrupt()
 270 {
 271     DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
 272             imsc, rawInt, maskInt());
 273
 274     if (maskInt()) {
 275         interrupt->raise();
 276         DPRINTF(Uart, " -- Generated\n");
 277     }
 278 }
 279
 280 void
 281 Pl011::setInterrupts(uint16_t ints, uint16_t mask)
 282 {
 283     const bool old_ints(!!maskInt());
 284
 285     imsc = mask;
 286     rawInt = ints;
 287
 288     if (!old_ints && maskInt()) {
 289         if (!intEvent.scheduled())
 290             schedule(intEvent, curTick() + intDelay);
 291     } else if (old_ints && !maskInt()) {
 292         interrupt->clear();
 293     }
 294 }
 295
 296
 297
 298 void
 299 Pl011::serialize(CheckpointOut &cp) const
 300 {
 301     DPRINTF(Checkpoint, "Serializing Arm PL011\n");
 302     SERIALIZE_SCALAR(control);
 303     SERIALIZE_SCALAR(fbrd);
 304     SERIALIZE_SCALAR(ibrd);
 305     SERIALIZE_SCALAR(lcrh);
 306     SERIALIZE_SCALAR(ifls);
 307
 308     // Preserve backwards compatibility by giving these silly names.
 309     paramOut(cp, "imsc_serial", imsc);
 310     paramOut(cp, "rawInt_serial", rawInt);
 311 }
 312
 313 void
 314 Pl011::unserialize(CheckpointIn &cp)
 315 {
 316     DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
 317
 318     UNSERIALIZE_SCALAR(control);
 319     UNSERIALIZE_SCALAR(fbrd);
 320     UNSERIALIZE_SCALAR(ibrd);
 321     UNSERIALIZE_SCALAR(lcrh);
 322     UNSERIALIZE_SCALAR(ifls);
 323
 324     // Preserve backwards compatibility by giving these silly names.
 325     paramIn(cp, "imsc_serial", imsc);
 326     paramIn(cp, "rawInt_serial", rawInt);
 327 }
 328
 329 Pl011 *
 330 Pl011Params::create()
 331 {
 332     return new Pl011(this);
 333 }