src/dev/arm/pl011.cc

   1 /*
   2  * Copyright (c) 2010, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "dev/arm/pl011.hh"
  42
  43 #include "base/trace.hh"
  44 #include "debug/Checkpoint.hh"
  45 #include "debug/Uart.hh"
  46 #include "dev/arm/amba_device.hh"
  47 #include "dev/arm/base_gic.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/packet_access.hh"
  50 #include "params/Pl011.hh"
  51 #include "sim/sim_exit.hh"
  52
  53 Pl011::Pl011(const Pl011Params &p)
  54     : Uart(p, 0x1000),
  55       intEvent([this]{ generateInterrupt(); }, name()),
  56       control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
  57       imsc(0), rawInt(0),
  58       endOnEOT(p.end_on_eot), interrupt(p.interrupt->get()),
  59       intDelay(p.int_delay)
  60 {
  61 }
  62
  63 Tick
  64 Pl011::read(PacketPtr pkt)
  65 {
  66     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  67     assert(pkt->getSize() <= 4);
  68
  69     Addr daddr = pkt->getAddr() - pioAddr;
  70
  71     DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
  72
  73     // use a temporary data since the uart registers are read/written with
  74     // different size operations
  75     //
  76     uint32_t data = 0;
  77
  78     switch(daddr) {
  79       case UART_DR:
  80         data = 0;
  81         if (device->dataAvailable()) {
  82             data = device->readData();
  83             // Since we don't simulate a FIFO for incoming data, we
  84             // assume it's empty and clear RXINTR and RTINTR.
  85             clearInterrupts(UART_RXINTR | UART_RTINTR);
  86             if (device->dataAvailable()) {
  87                 DPRINTF(Uart, "Re-raising interrupt due to more data "
  88                         "after UART_DR read\n");
  89                 dataAvailable();
  90             }
  91         }
  92         break;
  93       case UART_RSR:
  94         data = 0x0; // We never have errors
  95         break;
  96       case UART_FR:
  97         data =
  98             UART_FR_CTS | // Clear To Send
  99             // Given we do not simulate a FIFO we are either empty or full.
 100             (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
 101             UART_FR_TXFE; // TX FIFO empty
 102
 103         DPRINTF(Uart,
 104                 "Reading FR register as %#x rawInt=0x%x "
 105                 "imsc=0x%x maskInt=0x%x\n",
 106                 data, rawInt, imsc, maskInt());
 107         break;
 108       case UART_CR:
 109         data = control;
 110         break;
 111       case UART_IBRD:
 112         data = ibrd;
 113         break;
 114       case UART_FBRD:
 115         data = fbrd;
 116         break;
 117       case UART_LCRH:
 118         data = lcrh;
 119         break;
 120       case UART_IFLS:
 121         data = ifls;
 122         break;
 123       case UART_IMSC:
 124         data = imsc;
 125         break;
 126       case UART_RIS:
 127         data = rawInt;
 128         DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
 129         break;
 130       case UART_MIS:
 131         DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
 132         data = maskInt();
 133         break;
 134       case UART_DMACR:
 135         warn("PL011: DMA not supported\n");
 136         data = 0x0; // DMA never enabled
 137         break;
 138       default:
 139         if (readId(pkt, AMBA_ID, pioAddr)) {
 140             // Hack for variable size accesses
 141             data = pkt->getUintX(ByteOrder::little);
 142             break;
 143         }
 144
 145         panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
 146         break;
 147     }
 148
 149     pkt->setUintX(data, ByteOrder::little);
 150     pkt->makeAtomicResponse();
 151     return pioDelay;
 152 }
 153
 154 Tick
 155 Pl011::write(PacketPtr pkt)
 156 {
 157
 158     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 159     assert(pkt->getSize() <= 4);
 160
 161     Addr daddr = pkt->getAddr() - pioAddr;
 162
 163     DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
 164             pkt->getLE<uint8_t>(), pkt->getSize());
 165
 166     // use a temporary data since the uart registers are read/written with
 167     // different size operations
 168     //
 169     const uint32_t data = pkt->getUintX(ByteOrder::little);
 170
 171     switch (daddr) {
 172         case UART_DR:
 173           if ((data & 0xFF) == 0x04 && endOnEOT)
 174             exitSimLoop("UART received EOT", 0);
 175
 176         device->writeData(data & 0xFF);
 177         // We're supposed to clear TXINTR when this register is
 178         // written to, however. since we're also infinitely fast, we
 179         // need to immediately raise it again.
 180         clearInterrupts(UART_TXINTR);
 181         raiseInterrupts(UART_TXINTR);
 182         break;
 183       case UART_ECR: // clears errors, ignore
 184         break;
 185       case UART_CR:
 186         control = data;
 187         break;
 188       case UART_IBRD:
 189         ibrd = data;
 190         break;
 191       case UART_FBRD:
 192         fbrd = data;
 193         break;
 194       case UART_LCRH:
 195         lcrh = data;
 196         break;
 197       case UART_IFLS:
 198         ifls = data;
 199         break;
 200       case UART_IMSC:
 201         DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
 202         setInterruptMask(data);
 203         break;
 204
 205       case UART_ICR:
 206         DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
 207         clearInterrupts(data);
 208         if (device->dataAvailable()) {
 209             DPRINTF(Uart, "Re-raising interrupt due to more data after "
 210                     "UART_ICR write\n");
 211             dataAvailable();
 212         }
 213         break;
 214       case UART_DMACR:
 215         // DMA is not supported, so panic if anyome tries to enable it.
 216         // Bits 0, 1, 2 enables DMA on RX, TX, ERR respectively, others res0.
 217         if (data & 0x7) {
 218             panic("Tried to enable DMA on PL011\n");
 219         }
 220         warn("PL011: DMA not supported\n");
 221         break;
 222       default:
 223         panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
 224         break;
 225     }
 226     pkt->makeAtomicResponse();
 227     return pioDelay;
 228 }
 229
 230 void
 231 Pl011::dataAvailable()
 232 {
 233     /*@todo ignore the fifo, just say we have data now
 234      * We might want to fix this, or we might not care */
 235     DPRINTF(Uart, "Data available, scheduling interrupt\n");
 236     raiseInterrupts(UART_RXINTR | UART_RTINTR);
 237 }
 238
 239 void
 240 Pl011::generateInterrupt()
 241 {
 242     DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
 243             imsc, rawInt, maskInt());
 244
 245     if (maskInt()) {
 246         interrupt->raise();
 247         DPRINTF(Uart, " -- Generated\n");
 248     }
 249 }
 250
 251 void
 252 Pl011::setInterrupts(uint16_t ints, uint16_t mask)
 253 {
 254     const bool old_ints(!!maskInt());
 255
 256     imsc = mask;
 257     rawInt = ints;
 258
 259     if (!old_ints && maskInt()) {
 260         if (!intEvent.scheduled())
 261             schedule(intEvent, curTick() + intDelay);
 262     } else if (old_ints && !maskInt()) {
 263         interrupt->clear();
 264     }
 265 }
 266
 267
 268
 269 void
 270 Pl011::serialize(CheckpointOut &cp) const
 271 {
 272     DPRINTF(Checkpoint, "Serializing Arm PL011\n");
 273     SERIALIZE_SCALAR(control);
 274     SERIALIZE_SCALAR(fbrd);
 275     SERIALIZE_SCALAR(ibrd);
 276     SERIALIZE_SCALAR(lcrh);
 277     SERIALIZE_SCALAR(ifls);
 278
 279     // Preserve backwards compatibility by giving these silly names.
 280     paramOut(cp, "imsc_serial", imsc);
 281     paramOut(cp, "rawInt_serial", rawInt);
 282 }
 283
 284 void
 285 Pl011::unserialize(CheckpointIn &cp)
 286 {
 287     DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
 288
 289     UNSERIALIZE_SCALAR(control);
 290     UNSERIALIZE_SCALAR(fbrd);
 291     UNSERIALIZE_SCALAR(ibrd);
 292     UNSERIALIZE_SCALAR(lcrh);
 293     UNSERIALIZE_SCALAR(ifls);
 294
 295     // Preserve backwards compatibility by giving these silly names.
 296     paramIn(cp, "imsc_serial", imsc);
 297     paramIn(cp, "rawInt_serial", rawInt);
 298 }