src/dev/arm/pl111.hh

   1 /*
   2  * Copyright (c) 2010-2012, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: William Wang
  38  *          Ali Saidi
  39  */
  40
  41
  42 /** @file
  43  * Implementiation of a PL111 CLCD controller
  44  */
  45
  46 #ifndef __DEV_ARM_PL111_HH__
  47 #define __DEV_ARM_PL111_HH__
  48
  49 #include <fstream>
  50 #include <memory>
  51
  52 #include "base/bmpwriter.hh"
  53 #include "base/framebuffer.hh"
  54 #include "base/output.hh"
  55 #include "dev/arm/amba_device.hh"
  56 #include "params/Pl111.hh"
  57 #include "sim/serialize.hh"
  58
  59 class VncInput;
  60
  61 class Pl111: public AmbaDmaDevice
  62 {
  63   protected:
  64     static const uint64_t AMBA_ID       = ULL(0xb105f00d00141111);
  65     /** ARM PL111 register map*/
  66     static const int LcdTiming0       = 0x000;
  67     static const int LcdTiming1       = 0x004;
  68     static const int LcdTiming2       = 0x008;
  69     static const int LcdTiming3       = 0x00C;
  70     static const int LcdUpBase        = 0x010;
  71     static const int LcdLpBase        = 0x014;
  72     static const int LcdControl       = 0x018;
  73     static const int LcdImsc          = 0x01C;
  74     static const int LcdRis           = 0x020;
  75     static const int LcdMis           = 0x024;
  76     static const int LcdIcr           = 0x028;
  77     static const int LcdUpCurr        = 0x02C;
  78     static const int LcdLpCurr        = 0x030;
  79     static const int LcdPalette       = 0x200;
  80     static const int CrsrImage        = 0x800;
  81     static const int ClcdCrsrCtrl     = 0xC00;
  82     static const int ClcdCrsrConfig   = 0xC04;
  83     static const int ClcdCrsrPalette0 = 0xC08;
  84     static const int ClcdCrsrPalette1 = 0xC0C;
  85     static const int ClcdCrsrXY       = 0xC10;
  86     static const int ClcdCrsrClip     = 0xC14;
  87     static const int ClcdCrsrImsc     = 0xC20;
  88     static const int ClcdCrsrIcr      = 0xC24;
  89     static const int ClcdCrsrRis      = 0xC28;
  90     static const int ClcdCrsrMis      = 0xC2C;
  91
  92     static const int LcdPaletteSize   = 128;
  93     static const int CrsrImageSize    = 256;
  94
  95     static const int LcdMaxWidth      = 1024; // pixels per line
  96     static const int LcdMaxHeight     = 768;  // lines per panel
  97
  98     static const int dmaSize            = 8;    // 64 bits
  99     static const int maxOutstandingDma  = 16;   // 16 deep FIFO of 64 bits
 100
 101     static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
 102
 103     enum LcdMode {
 104         bpp1 = 0,
 105         bpp2,
 106         bpp4,
 107         bpp8,
 108         bpp16,
 109         bpp24,
 110         bpp16m565,
 111         bpp12
 112     };
 113
 114     BitUnion8(InterruptReg)
 115         Bitfield<1> underflow;
 116         Bitfield<2> baseaddr;
 117         Bitfield<3> vcomp;
 118         Bitfield<4> ahbmaster;
 119     EndBitUnion(InterruptReg)
 120
 121     BitUnion32(TimingReg0)
 122         Bitfield<7,2> ppl;
 123         Bitfield<15,8> hsw;
 124         Bitfield<23,16> hfp;
 125         Bitfield<31,24> hbp;
 126     EndBitUnion(TimingReg0)
 127
 128     BitUnion32(TimingReg1)
 129         Bitfield<9,0> lpp;
 130         Bitfield<15,10> vsw;
 131         Bitfield<23,16> vfp;
 132         Bitfield<31,24> vbp;
 133     EndBitUnion(TimingReg1)
 134
 135     BitUnion32(TimingReg2)
 136         Bitfield<4,0> pcdlo;
 137         Bitfield<5> clksel;
 138         Bitfield<10,6> acb;
 139         Bitfield<11> avs;
 140         Bitfield<12> ihs;
 141         Bitfield<13> ipc;
 142         Bitfield<14> ioe;
 143         Bitfield<25,16> cpl;
 144         Bitfield<26> bcd;
 145         Bitfield<31,27> pcdhi;
 146     EndBitUnion(TimingReg2)
 147
 148     BitUnion32(TimingReg3)
 149         Bitfield<6,0> led;
 150         Bitfield<16> lee;
 151     EndBitUnion(TimingReg3)
 152
 153     BitUnion32(ControlReg)
 154         Bitfield<0> lcden;
 155         Bitfield<3,1> lcdbpp;
 156         Bitfield<4> lcdbw;
 157         Bitfield<5> lcdtft;
 158         Bitfield<6> lcdmono8;
 159         Bitfield<7> lcddual;
 160         Bitfield<8> bgr;
 161         Bitfield<9> bebo;
 162         Bitfield<10> bepo;
 163         Bitfield<11> lcdpwr;
 164         Bitfield<13,12> lcdvcomp;
 165         Bitfield<16> watermark;
 166     EndBitUnion(ControlReg)
 167
 168     /**
 169      * Event wrapper for dmaDone()
 170      *
 171      * This event calls pushes its this pointer onto the freeDoneEvent
 172      * vector and calls dmaDone() when triggered.
 173      */
 174     class DmaDoneEvent : public Event
 175     {
 176       private:
 177         Pl111 &obj;
 178
 179       public:
 180         DmaDoneEvent(Pl111 *_obj)
 181             : Event(), obj(*_obj) {}
 182
 183         void process() {
 184             obj.dmaDoneEventFree.push_back(this);
 185             obj.dmaDone();
 186         }
 187
 188         const std::string name() const {
 189             return obj.name() + ".DmaDoneEvent";
 190         }
 191     };
 192
 193     /** Horizontal axis panel control register */
 194     TimingReg0 lcdTiming0;
 195
 196     /** Vertical axis panel control register */
 197     TimingReg1 lcdTiming1;
 198
 199     /** Clock and signal polarity control register */
 200     TimingReg2 lcdTiming2;
 201
 202     /** Line end control register */
 203     TimingReg3 lcdTiming3;
 204
 205     /** Upper panel frame base address register */
 206     uint32_t lcdUpbase;
 207
 208     /** Lower panel frame base address register */
 209     uint32_t lcdLpbase;
 210
 211     /** Control register */
 212     ControlReg lcdControl;
 213
 214     /** Interrupt mask set/clear register */
 215     InterruptReg lcdImsc;
 216
 217     /** Raw interrupt status register - const */
 218     InterruptReg lcdRis;
 219
 220     /** Masked interrupt status register */
 221     InterruptReg lcdMis;
 222
 223     /** 256x16-bit color palette registers
 224      * 256 palette entries organized as 128 locations of two entries per word */
 225     uint32_t lcdPalette[LcdPaletteSize];
 226
 227     /** Cursor image RAM register
 228      * 256-word wide values defining images overlaid by the hw cursor mechanism */
 229     uint32_t cursorImage[CrsrImageSize];
 230
 231     /** Cursor control register */
 232     uint32_t clcdCrsrCtrl;
 233
 234     /** Cursor configuration register */
 235     uint32_t clcdCrsrConfig;
 236
 237     /** Cursor palette registers */
 238     uint32_t clcdCrsrPalette0;
 239     uint32_t clcdCrsrPalette1;
 240
 241     /** Cursor XY position register */
 242     uint32_t clcdCrsrXY;
 243
 244     /** Cursor clip position register */
 245     uint32_t clcdCrsrClip;
 246
 247     /** Cursor interrupt mask set/clear register */
 248     InterruptReg clcdCrsrImsc;
 249
 250     /** Cursor interrupt clear register */
 251     InterruptReg clcdCrsrIcr;
 252
 253     /** Cursor raw interrupt status register - const */
 254     InterruptReg clcdCrsrRis;
 255
 256     /** Cursor masked interrupt status register - const */
 257     InterruptReg clcdCrsrMis;
 258
 259     /** Pixel clock */
 260     Tick pixelClock;
 261
 262     PixelConverter converter;
 263     FrameBuffer fb;
 264
 265     /** VNC server */
 266     VncInput *vnc;
 267
 268     /** Helper to write out bitmaps */
 269     BmpWriter bmp;
 270
 271     /** Picture of what the current frame buffer looks like */
 272     OutputStream *pic;
 273
 274     /** Frame buffer width - pixels per line */
 275     uint16_t width;
 276
 277     /** Frame buffer height - lines per panel */
 278     uint16_t height;
 279
 280     /** Bytes per pixel */
 281     uint8_t bytesPerPixel;
 282
 283     /** CLCDC supports up to 1024x768 */
 284     uint8_t *dmaBuffer;
 285
 286     /** Start time for frame buffer dma read */
 287     Tick startTime;
 288
 289     /** Frame buffer base address */
 290     Addr startAddr;
 291
 292     /** Frame buffer max address */
 293     Addr maxAddr;
 294
 295     /** Frame buffer current address */
 296     Addr curAddr;
 297
 298     /** DMA FIFO watermark */
 299     uint32_t waterMark;
 300
 301     /** Number of pending dma reads */
 302     uint32_t dmaPendingNum;
 303
 304     PixelConverter pixelConverter() const;
 305
 306     /** Send updated parameters to the vnc server */
 307     void updateVideoParams();
 308
 309     /** DMA framebuffer read */
 310     void readFramebuffer();
 311
 312     /** Generate dma framebuffer read event */
 313     void generateReadEvent();
 314
 315     /** Function to generate interrupt */
 316     void generateInterrupt();
 317
 318     /** fillFIFO event */
 319     void fillFifo();
 320
 321     /** start the dmas off after power is enabled */
 322     void startDma();
 323
 324     /** DMA done event */
 325     void dmaDone();
 326
 327     /** DMA framebuffer read event */
 328     EventFunctionWrapper readEvent;
 329
 330     /** Fill fifo */
 331     EventFunctionWrapper fillFifoEvent;
 332
 333     /**@{*/
 334     /**
 335      * All pre-allocated DMA done events
 336      *
 337      * The PL111 model preallocates maxOutstandingDma number of
 338      * DmaDoneEvents to avoid having to heap allocate every single
 339      * event when it is needed. In order to keep track of which events
 340      * are in flight and which are ready to be used, we use two
 341      * different vectors. dmaDoneEventAll contains <i>all</i>
 342      * DmaDoneEvents that the object may use, while dmaDoneEventFree
 343      * contains a list of currently <i>unused</i> events. When an
 344      * event needs to be scheduled, the last element of the
 345      * dmaDoneEventFree is used and removed from the list. When an
 346      * event fires, it is added to the end of the
 347      * dmaEventFreeList. dmaDoneEventAll is never used except for in
 348      * initialization and serialization.
 349      */
 350     std::vector<DmaDoneEvent> dmaDoneEventAll;
 351
 352     /** Unused DMA done events that are ready to be scheduled */
 353     std::vector<DmaDoneEvent *> dmaDoneEventFree;
 354     /**@}*/
 355
 356     /** Wrapper to create an event out of the interrupt */
 357     EventFunctionWrapper intEvent;
 358
 359     bool enableCapture;
 360
 361   public:
 362     typedef Pl111Params Params;
 363
 364     const Params *
 365     params() const
 366     {
 367         return dynamic_cast<const Params *>(_params);
 368     }
 369     Pl111(const Params *p);
 370     ~Pl111();
 371
 372     Tick read(PacketPtr pkt) override;
 373     Tick write(PacketPtr pkt) override;
 374
 375     void serialize(CheckpointOut &cp) const override;
 376     void unserialize(CheckpointIn &cp) override;
 377
 378     /**
 379      * Determine the address ranges that this device responds to.
 380      *
 381      * @return a list of non-overlapping address ranges
 382      */
 383     AddrRangeList getAddrRanges() const override;
 384 };
 385
 386 #endif