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37 * Authors: William Wang
43 * Implementiation of a PL111 CLCD controller
46 #ifndef __DEV_ARM_PL111_HH__
47 #define __DEV_ARM_PL111_HH__
52 #include "base/bitmap.hh"
53 #include "base/framebuffer.hh"
54 #include "dev/arm/amba_device.hh"
55 #include "params/Pl111.hh"
56 #include "sim/serialize.hh"
60 class Pl111: public AmbaDmaDevice
63 static const uint64_t AMBA_ID = ULL(0xb105f00d00141111);
64 /** ARM PL111 register map*/
65 static const int LcdTiming0 = 0x000;
66 static const int LcdTiming1 = 0x004;
67 static const int LcdTiming2 = 0x008;
68 static const int LcdTiming3 = 0x00C;
69 static const int LcdUpBase = 0x010;
70 static const int LcdLpBase = 0x014;
71 static const int LcdControl = 0x018;
72 static const int LcdImsc = 0x01C;
73 static const int LcdRis = 0x020;
74 static const int LcdMis = 0x024;
75 static const int LcdIcr = 0x028;
76 static const int LcdUpCurr = 0x02C;
77 static const int LcdLpCurr = 0x030;
78 static const int LcdPalette = 0x200;
79 static const int CrsrImage = 0x800;
80 static const int ClcdCrsrCtrl = 0xC00;
81 static const int ClcdCrsrConfig = 0xC04;
82 static const int ClcdCrsrPalette0 = 0xC08;
83 static const int ClcdCrsrPalette1 = 0xC0C;
84 static const int ClcdCrsrXY = 0xC10;
85 static const int ClcdCrsrClip = 0xC14;
86 static const int ClcdCrsrImsc = 0xC20;
87 static const int ClcdCrsrIcr = 0xC24;
88 static const int ClcdCrsrRis = 0xC28;
89 static const int ClcdCrsrMis = 0xC2C;
91 static const int LcdPaletteSize = 128;
92 static const int CrsrImageSize = 256;
94 static const int LcdMaxWidth = 1024; // pixels per line
95 static const int LcdMaxHeight = 768; // lines per panel
97 static const int dmaSize = 8; // 64 bits
98 static const int maxOutstandingDma = 16; // 16 deep FIFO of 64 bits
100 static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
113 BitUnion8(InterruptReg)
114 Bitfield<1> underflow;
115 Bitfield<2> baseaddr;
117 Bitfield<4> ahbmaster;
118 EndBitUnion(InterruptReg)
120 BitUnion32(TimingReg0)
125 EndBitUnion(TimingReg0)
127 BitUnion32(TimingReg1)
132 EndBitUnion(TimingReg1)
134 BitUnion32(TimingReg2)
144 Bitfield<31,27> pcdhi;
145 EndBitUnion(TimingReg2)
147 BitUnion32(TimingReg3)
150 EndBitUnion(TimingReg3)
152 BitUnion32(ControlReg)
154 Bitfield<3,1> lcdbpp;
157 Bitfield<6> lcdmono8;
163 Bitfield<13,12> lcdvcomp;
164 Bitfield<16> watermark;
165 EndBitUnion(ControlReg)
168 * Event wrapper for dmaDone()
170 * This event calls pushes its this pointer onto the freeDoneEvent
171 * vector and calls dmaDone() when triggered.
173 class DmaDoneEvent : public Event
179 DmaDoneEvent(Pl111 *_obj)
180 : Event(), obj(*_obj) {}
183 obj.dmaDoneEventFree.push_back(this);
187 const std::string name() const {
188 return obj.name() + ".DmaDoneEvent";
192 /** Horizontal axis panel control register */
193 TimingReg0 lcdTiming0;
195 /** Vertical axis panel control register */
196 TimingReg1 lcdTiming1;
198 /** Clock and signal polarity control register */
199 TimingReg2 lcdTiming2;
201 /** Line end control register */
202 TimingReg3 lcdTiming3;
204 /** Upper panel frame base address register */
207 /** Lower panel frame base address register */
210 /** Control register */
211 ControlReg lcdControl;
213 /** Interrupt mask set/clear register */
214 InterruptReg lcdImsc;
216 /** Raw interrupt status register - const */
219 /** Masked interrupt status register */
222 /** 256x16-bit color palette registers
223 * 256 palette entries organized as 128 locations of two entries per word */
224 uint32_t lcdPalette[LcdPaletteSize];
226 /** Cursor image RAM register
227 * 256-word wide values defining images overlaid by the hw cursor mechanism */
228 uint32_t cursorImage[CrsrImageSize];
230 /** Cursor control register */
231 uint32_t clcdCrsrCtrl;
233 /** Cursor configuration register */
234 uint32_t clcdCrsrConfig;
236 /** Cursor palette registers */
237 uint32_t clcdCrsrPalette0;
238 uint32_t clcdCrsrPalette1;
240 /** Cursor XY position register */
243 /** Cursor clip position register */
244 uint32_t clcdCrsrClip;
246 /** Cursor interrupt mask set/clear register */
247 InterruptReg clcdCrsrImsc;
249 /** Cursor interrupt clear register */
250 InterruptReg clcdCrsrIcr;
252 /** Cursor raw interrupt status register - const */
253 InterruptReg clcdCrsrRis;
255 /** Cursor masked interrupt status register - const */
256 InterruptReg clcdCrsrMis;
261 PixelConverter converter;
267 /** Helper to write out bitmaps */
270 /** Picture of what the current frame buffer looks like */
273 /** Frame buffer width - pixels per line */
276 /** Frame buffer height - lines per panel */
279 /** Bytes per pixel */
280 uint8_t bytesPerPixel;
282 /** CLCDC supports up to 1024x768 */
285 /** Start time for frame buffer dma read */
288 /** Frame buffer base address */
291 /** Frame buffer max address */
294 /** Frame buffer current address */
297 /** DMA FIFO watermark */
300 /** Number of pending dma reads */
301 uint32_t dmaPendingNum;
303 PixelConverter pixelConverter() const;
305 /** Send updated parameters to the vnc server */
306 void updateVideoParams();
308 /** DMA framebuffer read */
309 void readFramebuffer();
311 /** Generate dma framebuffer read event */
312 void generateReadEvent();
314 /** Function to generate interrupt */
315 void generateInterrupt();
317 /** fillFIFO event */
320 /** start the dmas off after power is enabled */
323 /** DMA done event */
326 /** DMA framebuffer read event */
327 EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent;
330 EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
334 * All pre-allocated DMA done events
336 * The PL111 model preallocates maxOutstandingDma number of
337 * DmaDoneEvents to avoid having to heap allocate every single
338 * event when it is needed. In order to keep track of which events
339 * are in flight and which are ready to be used, we use two
340 * different vectors. dmaDoneEventAll contains <i>all</i>
341 * DmaDoneEvents that the object may use, while dmaDoneEventFree
342 * contains a list of currently <i>unused</i> events. When an
343 * event needs to be scheduled, the last element of the
344 * dmaDoneEventFree is used and removed from the list. When an
345 * event fires, it is added to the end of the
346 * dmaEventFreeList. dmaDoneEventAll is never used except for in
347 * initialization and serialization.
349 std::vector<DmaDoneEvent> dmaDoneEventAll;
351 /** Unused DMA done events that are ready to be scheduled */
352 std::vector<DmaDoneEvent *> dmaDoneEventFree;
355 /** Wrapper to create an event out of the interrupt */
356 EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
361 typedef Pl111Params Params;
366 return dynamic_cast<const Params *>(_params);
368 Pl111(const Params *p);
371 Tick read(PacketPtr pkt) override;
372 Tick write(PacketPtr pkt) override;
374 void serialize(CheckpointOut &cp) const override;
375 void unserialize(CheckpointIn &cp) override;
378 * Determine the address ranges that this device responds to.
380 * @return a list of non-overlapping address ranges
382 AddrRangeList getAddrRanges() const override;