ARM: Add checkpointing support
[gem5.git] / src / dev / arm / rv_ctrl.cc
1 /*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40 #include "base/trace.hh"
41 #include "dev/arm/rv_ctrl.hh"
42 #include "mem/packet.hh"
43 #include "mem/packet_access.hh"
44
45 RealViewCtrl::RealViewCtrl(Params *p)
46 : BasicPioDevice(p)
47 {
48 pioSize = 0xD4;
49 }
50
51 Tick
52 RealViewCtrl::read(PacketPtr pkt)
53 {
54 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
55 assert(pkt->getSize() == 4);
56 Addr daddr = pkt->getAddr() - pioAddr;
57 pkt->allocate();
58
59 switch(daddr) {
60 case ProcId:
61 pkt->set(params()->proc_id);
62 break;
63 case Clock24:
64 Tick clk;
65 clk = (Tick)(curTick / (24 * SimClock::Float::MHz));
66 pkt->set((uint32_t)(clk));
67 break;
68 case Flash:
69 pkt->set<uint32_t>(0);
70 break;
71 default:
72 panic("Tried to read RealView I/O at offset %#x that doesn't exist\n", daddr);
73 break;
74 }
75 pkt->makeAtomicResponse();
76 return pioDelay;
77
78 }
79
80 Tick
81 RealViewCtrl::write(PacketPtr pkt)
82 {
83 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
84
85 Addr daddr = pkt->getAddr() - pioAddr;
86 switch (daddr) {
87 case Flash:
88 break;
89 default:
90 panic("Tried to write RVIO at offset %#x that doesn't exist\n", daddr);
91 break;
92 }
93 pkt->makeAtomicResponse();
94 return pioDelay;
95 }
96
97 void
98 RealViewCtrl::serialize(std::ostream &os)
99 {
100 }
101
102 void
103 RealViewCtrl::unserialize(Checkpoint *cp, const std::string &section)
104 {
105 }
106
107 RealViewCtrl *
108 RealViewCtrlParams::create()
109 {
110 return new RealViewCtrl(this);
111 }