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40 #include "base/trace.hh"
41 #include "debug/RVCTRL.hh"
42 #include "dev/arm/rv_ctrl.hh"
43 #include "mem/packet.hh"
44 #include "mem/packet_access.hh"
46 RealViewCtrl::RealViewCtrl(Params
*p
)
47 : BasicPioDevice(p
, 0xD4), flags(0), scData(0)
52 RealViewCtrl::read(PacketPtr pkt
)
54 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
55 assert(pkt
->getSize() == 4);
56 Addr daddr
= pkt
->getAddr() - pioAddr
;
60 pkt
->set(params()->proc_id0
);
63 pkt
->set(params()->proc_id1
);
67 clk
= SimClock::Float::MHz
* curTick() * 24;
68 pkt
->set((uint32_t)(clk
));
72 clk100
= SimClock::Float::MHz
* curTick() * 100;
73 pkt
->set((uint32_t)(clk100
));
76 pkt
->set
<uint32_t>(0);
79 pkt
->set
<uint32_t>(0x00001F00);
82 pkt
->set
<uint32_t>(0x00012C5C);
85 pkt
->set
<uint32_t>(0x00002CC0);
88 pkt
->set
<uint32_t>(0x00002C75);
91 pkt
->set
<uint32_t>(0x00020211);
94 pkt
->set
<uint32_t>(0x00002C75);
97 pkt
->set
<uint32_t>(sysLock
);
100 pkt
->set
<uint32_t>(flags
);
103 pkt
->set
<uint32_t>(params()->idreg
);
106 pkt
->set
<uint32_t>(1);
109 pkt
->set
<uint32_t>(scData
);
110 DPRINTF(RVCTRL
, "Read %#x from SCReg\n", scData
);
113 pkt
->set
<uint32_t>(0); // not busy
114 DPRINTF(RVCTRL
, "Read 0 from CfgCtrl\n");
117 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
119 pkt
->set
<uint32_t>(0);
122 pkt
->makeAtomicResponse();
128 RealViewCtrl::write(PacketPtr pkt
)
130 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
132 Addr daddr
= pkt
->getAddr() - pioAddr
;
143 sysLock
.lockVal
= pkt
->get
<uint16_t>();
146 flags
= pkt
->get
<uint32_t>();
152 scData
= pkt
->get
<uint32_t>();
155 // A request is being submitted to read/write the system control
157 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
158 // For now, model as much of the OSC regs (can't find docs) as Linux
159 // seems to require (can't find docs); some clocks are deemed to be 0,
160 // giving all kinds of /0 problems booting Linux 3.9. Return a
161 // vaguely plausible number within the range the device trees state:
162 uint32_t data
= pkt
->get
<uint32_t>();
163 uint16_t dev
= bits(data
, 11, 0);
164 uint8_t pos
= bits(data
, 15, 12);
165 uint8_t site
= bits(data
, 17, 16);
166 uint8_t func
= bits(data
, 25, 20);
167 uint8_t dcc
= bits(data
, 29, 26);
168 bool wr
= bits(data
, 30);
169 bool start
= bits(data
, 31);
173 warn_once("SCReg: Writing %#x to dcc%d:site%d:pos%d:fn%d:dev%d\n",
174 scData
, dcc
, site
, pos
, func
, dev
);
175 // Only really support reading, for now!
177 // Only deal with function 1 (oscillators) so far!
178 if (dcc
!= 0 || pos
!= 0 || func
!= 1) {
179 warn("SCReg: read from unknown area "
180 "(dcc %d:site%d:pos%d:fn%d:dev%d)\n",
181 dcc
, site
, pos
, func
, dev
);
184 case 0: { // Motherboard regs
192 case 2: // PeriphClk 24MHz
197 warn("SCReg: read from unknown dev %d "
198 "(site%d:pos%d:fn%d)\n",
199 dev
, site
, pos
, func
);
202 case 1: { // Coretile 1 regs
204 case 0: // CPU PLL ref
207 case 4: // Muxed AXI master clock
216 case 7: // SYS PLL (also used for pl011 UART!)
219 case 8: // DDR PLL 40MHz fixed
224 warn("SCReg: read from unknown dev %d "
225 "(site%d:pos%d:fn%d)\n",
226 dev
, site
, pos
, func
);
230 warn("SCReg: Read from unknown site %d (pos%d:fn%d:dev%d)\n",
231 site
, pos
, func
, dev
);
233 DPRINTF(RVCTRL
, "SCReg: Will read %#x (ctrlWr %#x)\n", scData
, data
);
237 DPRINTF(RVCTRL
, "SCReg: write %#x to ctrl but not starting\n", data
);
240 case CfgStat
: // Weird to write this
242 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
243 daddr
, pkt
->get
<uint32_t>());
246 pkt
->makeAtomicResponse();
251 RealViewCtrl::serialize(std::ostream
&os
)
253 SERIALIZE_SCALAR(flags
);
257 RealViewCtrl::unserialize(Checkpoint
*cp
, const std::string
§ion
)
259 UNSERIALIZE_SCALAR(flags
);
263 RealViewCtrlParams::create()
265 return new RealViewCtrl(this);