src/dev/arm/smmu_v3.hh

   1 /*
   2  * Copyright (c) 2013, 2018-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __DEV_ARM_SMMU_V3_HH__
  39 #define __DEV_ARM_SMMU_V3_HH__
  40
  41 #include <list>
  42 #include <map>
  43 #include <queue>
  44 #include <string>
  45 #include <vector>
  46
  47 #include "base/statistics.hh"
  48 #include "dev/arm/smmu_v3_caches.hh"
  49 #include "dev/arm/smmu_v3_cmdexec.hh"
  50 #include "dev/arm/smmu_v3_defs.hh"
  51 #include "dev/arm/smmu_v3_deviceifc.hh"
  52 #include "dev/arm/smmu_v3_events.hh"
  53 #include "dev/arm/smmu_v3_ports.hh"
  54 #include "dev/arm/smmu_v3_proc.hh"
  55 #include "dev/arm/smmu_v3_ptops.hh"
  56 #include "mem/packet.hh"
  57 #include "params/SMMUv3.hh"
  58 #include "sim/clocked_object.hh"
  59 #include "sim/eventq.hh"
  60
  61 /**
  62  * @file:
  63  * This is an implementation of the SMMUv3 architecture.
  64  *
  65  * What can it do?
  66  * - Single-stage and nested translation with 4k or 64k granule.  16k would
  67  *   be straightforward to add.
  68  * - Large pages are supported.
  69  * - Works with any gem5 device as long as it is issuing packets with a
  70  *   valid (Sub)StreamId
  71  *
  72  * What it can't do?
  73  * - Fragment stage 1 page when the underlying stage 2 page is smaller.  S1
  74  *   page size > S2 page size is not supported
  75  * - Invalidations take zero time. This wouldn't be hard to fix.
  76  * - Checkpointing is not supported
  77  * - Stall/resume for faulting transactions is not supported
  78  */
  79 class SMMUTranslationProcess;
  80
  81 class SMMUv3 : public ClockedObject
  82 {
  83   protected:
  84
  85     friend class SMMUProcess;
  86     friend class SMMUTranslationProcess;
  87     friend class SMMUCommandExecProcess;
  88     friend class SMMUv3DeviceInterface;
  89
  90     const System &system;
  91     const RequestorID requestorId;
  92
  93     SMMURequestPort    requestPort;
  94     SMMUTableWalkPort tableWalkPort;
  95     SMMUControlPort   controlPort;
  96
  97     ARMArchTLB  tlb;
  98     ConfigCache configCache;
  99     IPACache    ipaCache;
 100     WalkCache   walkCache;
 101
 102     const bool tlbEnable;
 103     const bool configCacheEnable;
 104     const bool ipaCacheEnable;
 105     const bool walkCacheEnable;
 106     bool tableWalkPortEnable;
 107
 108     const bool walkCacheNonfinalEnable;
 109     const unsigned walkCacheS1Levels;
 110     const unsigned walkCacheS2Levels;
 111     const unsigned requestPortWidth; // in bytes
 112
 113     SMMUSemaphore tlbSem;
 114     SMMUSemaphore ifcSmmuSem;
 115     SMMUSemaphore smmuIfcSem;
 116     SMMUSemaphore configSem;
 117     SMMUSemaphore ipaSem;
 118     SMMUSemaphore walkSem;
 119     SMMUSemaphore requestPortSem;
 120
 121     SMMUSemaphore transSem; // max N transactions in SMMU
 122     SMMUSemaphore ptwSem; // max N concurrent PTWs
 123     SMMUSemaphore cycleSem; // max 1 table walk per cycle
 124
 125     // Timing parameters
 126     const Cycles tlbLat;
 127     const Cycles ifcSmmuLat;
 128     const Cycles smmuIfcLat;
 129     const Cycles configLat;
 130     const Cycles ipaLat;
 131     const Cycles walkLat;
 132
 133     // Stats
 134     Stats::Scalar steL1Fetches;
 135     Stats::Scalar steFetches;
 136     Stats::Scalar cdL1Fetches;
 137     Stats::Scalar cdFetches;
 138     Stats::Distribution translationTimeDist;
 139     Stats::Distribution ptwTimeDist;
 140
 141     std::vector<SMMUv3DeviceInterface *> deviceInterfaces;
 142
 143     SMMUCommandExecProcess commandExecutor;
 144
 145     const AddrRange regsMap;
 146     SMMURegs regs;
 147
 148     bool inSecureBlock(uint32_t offs) const;
 149
 150     std::queue<SMMUAction> packetsToRetry;
 151     std::queue<SMMUAction> packetsTableWalkToRetry;
 152
 153
 154     void scheduleDeviceRetries();
 155
 156     SMMUAction runProcess(SMMUProcess *proc, PacketPtr pkt);
 157     SMMUAction runProcessAtomic(SMMUProcess *proc, PacketPtr pkt);
 158     SMMUAction runProcessTiming(SMMUProcess *proc, PacketPtr pkt);
 159
 160     void processCommands();
 161     EventWrapper<SMMUv3, &SMMUv3::processCommands> processCommandsEvent;
 162
 163     void processCommand(const SMMUCommand &cmd);
 164
 165     const PageTableOps *getPageTableOps(uint8_t trans_granule);
 166
 167   public:
 168     SMMUv3(SMMUv3Params *p);
 169     virtual ~SMMUv3() {}
 170
 171     virtual void init() override;
 172     virtual void regStats() override;
 173
 174     Tick recvAtomic(PacketPtr pkt, PortID id);
 175     bool recvTimingReq(PacketPtr pkt, PortID id);
 176     bool recvTimingResp(PacketPtr pkt);
 177     void recvReqRetry();
 178
 179     bool tableWalkRecvTimingResp(PacketPtr pkt);
 180     void tableWalkRecvReqRetry();
 181
 182     Tick readControl(PacketPtr pkt);
 183     Tick writeControl(PacketPtr pkt);
 184
 185     DrainState drain() override;
 186     void serialize(CheckpointOut &cp) const override;
 187     void unserialize(CheckpointIn &cp) override;
 188
 189     virtual Port &getPort(const std::string &name,
 190                           PortID id = InvalidPortID) override;
 191 };
 192
 193 #endif /* __DEV_ARM_SMMU_V3_HH__ */