src/dev/arm/smmu_v3_ports.cc

   1 /*
   2  * Copyright (c) 2013, 2018-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "dev/arm/smmu_v3_ports.hh"
  39
  40 #include "base/logging.hh"
  41 #include "dev/arm/smmu_v3.hh"
  42 #include "dev/arm/smmu_v3_slaveifc.hh"
  43
  44 SMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) :
  45     MasterPort(_name, &_smmu),
  46     smmu(_smmu)
  47 {}
  48
  49 bool
  50 SMMUMasterPort::recvTimingResp(PacketPtr pkt)
  51 {
  52     return smmu.masterRecvTimingResp(pkt);
  53 }
  54
  55 void
  56 SMMUMasterPort::recvReqRetry()
  57 {
  58     return smmu.masterRecvReqRetry();
  59 }
  60
  61 SMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name,
  62                                                  SMMUv3 &_smmu) :
  63     MasterPort(_name, &_smmu),
  64     smmu(_smmu)
  65 {}
  66
  67 bool
  68 SMMUMasterTableWalkPort::recvTimingResp(PacketPtr pkt)
  69 {
  70     return smmu.masterTableWalkRecvTimingResp(pkt);
  71 }
  72
  73 void
  74 SMMUMasterTableWalkPort::recvReqRetry()
  75 {
  76     return smmu.masterTableWalkRecvReqRetry();
  77 }
  78
  79 SMMUSlavePort::SMMUSlavePort(const std::string &_name,
  80                              SMMUv3SlaveInterface &_ifc,
  81                              PortID _id)
  82 :
  83     QueuedSlavePort(_name, &_ifc, respQueue, _id),
  84     ifc(_ifc),
  85     respQueue(_ifc, *this)
  86 {}
  87
  88 void
  89 SMMUSlavePort::recvFunctional(PacketPtr pkt)
  90 {
  91     if (!respQueue.trySatisfyFunctional(pkt))
  92         recvAtomic(pkt);
  93 }
  94
  95 Tick
  96 SMMUSlavePort::recvAtomic(PacketPtr pkt)
  97 {
  98     return ifc.recvAtomic(pkt);
  99 }
 100
 101 bool
 102 SMMUSlavePort::recvTimingReq(PacketPtr pkt)
 103 {
 104     return ifc.recvTimingReq(pkt);
 105 }
 106
 107 SMMUControlPort::SMMUControlPort(const std::string &_name,
 108                                  SMMUv3 &_smmu, AddrRange _addrRange)
 109 :
 110     SimpleTimingPort(_name, &_smmu),
 111     smmu(_smmu),
 112     addrRange(_addrRange)
 113 {}
 114
 115 Tick
 116 SMMUControlPort::recvAtomic(PacketPtr pkt)
 117 {
 118     Addr addr = pkt->getAddr();
 119     unsigned size = pkt->getSize();
 120
 121     if (!addrRange.contains(addr) || !addrRange.contains(addr+size))
 122         panic("SMMU: invalid address on control port %x, packet size %d",
 123                 addr, size);
 124
 125     // @todo: We need to pay for this and not just zero it out
 126     pkt->headerDelay = pkt->payloadDelay = 0;
 127
 128     return pkt->isRead() ? smmu.readControl(pkt) : smmu.writeControl(pkt);
 129 }
 130
 131 AddrRangeList
 132 SMMUControlPort::getAddrRanges() const
 133 {
 134     AddrRangeList list;
 135     list.push_back(addrRange);
 136     return list;
 137 }
 138
 139 SMMUATSMasterPort::SMMUATSMasterPort(const std::string &_name,
 140                                      SMMUv3SlaveInterface &_ifc) :
 141     QueuedMasterPort(_name, &_ifc, reqQueue, snoopRespQueue),
 142     ifc(_ifc),
 143     reqQueue(_ifc, *this),
 144     snoopRespQueue(_ifc, *this)
 145 {}
 146
 147 bool
 148 SMMUATSMasterPort::recvTimingResp(PacketPtr pkt)
 149 {
 150     return ifc.atsMasterRecvTimingResp(pkt);
 151 }
 152
 153 SMMUATSSlavePort::SMMUATSSlavePort(const std::string &_name,
 154                                    SMMUv3SlaveInterface &_ifc) :
 155     QueuedSlavePort(_name, &_ifc, respQueue),
 156     ifc(_ifc),
 157     respQueue(_ifc, *this)
 158 {}
 159
 160 void
 161 SMMUATSSlavePort::recvFunctional(PacketPtr pkt)
 162 {
 163     panic("Functional access on ATS port!");
 164 }
 165
 166 Tick
 167 SMMUATSSlavePort::recvAtomic(PacketPtr pkt)
 168 {
 169     return ifc.atsSlaveRecvAtomic(pkt);
 170 }
 171
 172 bool
 173 SMMUATSSlavePort::recvTimingReq(PacketPtr pkt)
 174 {
 175     return ifc.atsSlaveRecvTimingReq(pkt);
 176 }