src/dev/arm/smmu_v3_slaveifc.hh

   1 /*
   2  * Copyright (c) 2013, 2018-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
  39 #define __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
  40
  41 #include <list>
  42
  43 #include "dev/arm/smmu_v3_caches.hh"
  44 #include "dev/arm/smmu_v3_defs.hh"
  45 #include "dev/arm/smmu_v3_events.hh"
  46 #include "dev/arm/smmu_v3_ports.hh"
  47 #include "dev/arm/smmu_v3_proc.hh"
  48 #include "params/SMMUv3SlaveInterface.hh"
  49 #include "sim/clocked_object.hh"
  50
  51 class SMMUTranslationProcess;
  52 class SMMUv3;
  53 class SMMUSlavePort;
  54
  55 class SMMUv3SlaveInterface : public ClockedObject
  56 {
  57   protected:
  58     friend class SMMUTranslationProcess;
  59
  60   public:
  61     SMMUv3 *smmu;
  62     SMMUTLB* microTLB;
  63     SMMUTLB* mainTLB;
  64
  65     const bool microTLBEnable;
  66     const bool mainTLBEnable;
  67
  68     SMMUSemaphore slavePortSem;
  69     SMMUSemaphore microTLBSem;
  70     SMMUSemaphore mainTLBSem;
  71
  72     const Cycles microTLBLat;
  73     const Cycles mainTLBLat;
  74
  75     SMMUSlavePort *slavePort;
  76     SMMUATSSlavePort  atsSlavePort;
  77     SMMUATSMasterPort atsMasterPort;
  78
  79     // in bytes
  80     const unsigned portWidth;
  81
  82     unsigned wrBufSlotsRemaining;
  83     unsigned xlateSlotsRemaining;
  84     unsigned pendingMemAccesses;
  85
  86     const bool prefetchEnable;
  87     const bool prefetchReserveLastWay;
  88
  89     std::list<SMMUTranslationProcess *> duplicateReqs;
  90     SMMUSignal duplicateReqRemoved;
  91
  92     std::list<SMMUTranslationProcess *> dependentReads[SMMU_MAX_TRANS_ID];
  93     std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID];
  94     SMMUSignal dependentReqRemoved;
  95
  96     // Receiving translation requests from the master device
  97     Tick recvAtomic(PacketPtr pkt);
  98     bool recvTimingReq(PacketPtr pkt);
  99     void schedTimingResp(PacketPtr pkt);
 100
 101     Tick atsSlaveRecvAtomic(PacketPtr pkt);
 102     bool atsSlaveRecvTimingReq(PacketPtr pkt);
 103     bool atsMasterRecvTimingResp(PacketPtr pkt);
 104     void schedAtsTimingResp(PacketPtr pkt);
 105
 106     void scheduleDeviceRetry();
 107     void sendDeviceRetry();
 108     void atsSendDeviceRetry();
 109
 110     bool deviceNeedsRetry;
 111     bool atsDeviceNeedsRetry;
 112
 113     SMMUDeviceRetryEvent sendDeviceRetryEvent;
 114     EventWrapper<
 115         SMMUv3SlaveInterface,
 116         &SMMUv3SlaveInterface::atsSendDeviceRetry> atsSendDeviceRetryEvent;
 117
 118     Port& getPort(const std::string &name, PortID id) override;
 119
 120   public:
 121     SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p);
 122
 123     ~SMMUv3SlaveInterface()
 124     {
 125         delete microTLB;
 126         delete mainTLB;
 127     }
 128
 129     const SMMUv3SlaveInterfaceParams *
 130     params() const
 131     {
 132         return static_cast<const SMMUv3SlaveInterfaceParams *>(_params);
 133     }
 134
 135     DrainState drain() override;
 136
 137     void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; }
 138     void sendRange();
 139 };
 140
 141 #endif /* __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ */