src/dev/arm/smmu_v3_transl.hh

   1 /*
   2  * Copyright (c) 2013, 2018-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __DEV_ARM_SMMU_V3_TRANSL_HH__
  39 #define __DEV_ARM_SMMU_V3_TRANSL_HH__
  40
  41 #include "base/compiler.hh"
  42 #include "dev/arm/smmu_v3_deviceifc.hh"
  43 #include "dev/arm/smmu_v3_proc.hh"
  44 #include "dev/arm/smmu_v3_ptops.hh"
  45 #include "mem/packet.hh"
  46
  47 struct SMMUTranslRequest
  48 {
  49     Addr     addr;
  50     unsigned size;
  51     uint32_t sid;  // streamId
  52     uint32_t ssid; // substreamId
  53     bool     isWrite;
  54     bool     isPrefetch;
  55     bool     isAtsRequest;
  56
  57     PacketPtr pkt;
  58
  59     static SMMUTranslRequest fromPacket(PacketPtr pkt, bool ats = false);
  60     static SMMUTranslRequest prefetch(Addr addr, uint32_t sid, uint32_t ssid);
  61 };
  62
  63 class SMMUTranslationProcess : public SMMUProcess
  64 {
  65   private:
  66     struct TranslContext
  67     {
  68         bool stage1Enable;
  69         bool stage2Enable;
  70         Addr ttb0, ttb1, httb;
  71         uint16_t asid;
  72         uint16_t vmid;
  73         uint8_t stage1TranslGranule;
  74         uint8_t stage2TranslGranule;
  75         uint8_t t0sz;
  76         uint8_t s2t0sz;
  77     };
  78
  79     enum FaultType
  80     {
  81         FAULT_NONE,
  82         FAULT_TRANSLATION, // F_TRANSLATION
  83         FAULT_PERMISSION,  // F_PERMISSION
  84     };
  85
  86     struct TranslResult
  87     {
  88         FaultType  fault;
  89         Addr       addr;
  90         Addr       addrMask;
  91         bool       writable;
  92     };
  93
  94     SMMUv3DeviceInterface &ifc;
  95
  96     SMMUTranslRequest request;
  97     TranslContext context;
  98
  99     Tick recvTick;
 100     Tick M5_CLASS_VAR_USED faultTick;
 101
 102     virtual void main(Yield &yield);
 103
 104     TranslResult bypass(Addr addr) const;
 105     TranslResult smmuTranslation(Yield &yield);
 106
 107     bool microTLBLookup(Yield &yield, TranslResult &tr);
 108     bool ifcTLBLookup(Yield &yield, TranslResult &tr, bool &wasPrefetched);
 109     bool smmuTLBLookup(Yield &yield, TranslResult &tr);
 110
 111     void microTLBUpdate(Yield &yield, const TranslResult &tr);
 112     void ifcTLBUpdate(Yield &yield, const TranslResult &tr);
 113     void smmuTLBUpdate(Yield &yield, const TranslResult &tr);
 114
 115     bool configCacheLookup(Yield &yield, TranslContext &tc);
 116     void configCacheUpdate(Yield &yield, const TranslContext &tc);
 117     bool findConfig(Yield &yield, TranslContext &tc, TranslResult &tr);
 118
 119     void walkCacheLookup(Yield &yield,
 120                          const WalkCache::Entry *&walkEntry,
 121                          Addr addr, uint16_t asid, uint16_t vmid,
 122                          unsigned stage, unsigned level);
 123
 124     void walkCacheUpdate(Yield &yield, Addr va, Addr vaMask, Addr pa,
 125                          unsigned stage, unsigned level,
 126                          bool leaf, uint8_t permissions);
 127
 128     TranslResult walkStage1And2(Yield &yield, Addr addr,
 129                                 const PageTableOps *pt_ops,
 130                                 unsigned level, Addr walkPtr);
 131
 132     TranslResult walkStage2(Yield &yield, Addr addr, bool final_tr,
 133                             const PageTableOps *pt_ops,
 134                             unsigned level, Addr walkPtr);
 135
 136     TranslResult translateStage1And2(Yield &yield, Addr addr);
 137     TranslResult translateStage2(Yield &yield, Addr addr, bool final_tr);
 138
 139     TranslResult combineTranslations(const TranslResult &s1tr,
 140                                      const TranslResult &s2tr) const;
 141
 142     /**
 143      * Used to force ordering on transactions with same
 144      * (SID, SSID, 4k page) to avoid multiple identical
 145      * page-table walks.
 146      */
 147     bool hazard4kCheck();
 148     void hazard4kRegister();
 149     void hazard4kHold(Yield &yield);
 150     void hazard4kRelease();
 151
 152     /**
 153      * Used to force ordering on transactions with the same orderId.
 154      * This attempts to model AXI IDs.
 155      */
 156     void hazardIdRegister();
 157     void hazardIdHold(Yield &yield);
 158     void hazardIdRelease();
 159
 160     void issuePrefetch(Addr addr);
 161
 162     void completeTransaction(Yield &yield, const TranslResult &tr);
 163     void completePrefetch(Yield &yield);
 164
 165     void sendEvent(Yield &yield, const SMMUEvent &ev);
 166
 167     void doReadSTE(Yield &yield, StreamTableEntry &ste, uint32_t sid);
 168     void doReadCD(Yield &yield, ContextDescriptor &cd,
 169                   const StreamTableEntry &ste, uint32_t sid, uint32_t ssid);
 170     void doReadConfig(Yield &yield, Addr addr, void *ptr, size_t size,
 171                       uint32_t sid, uint32_t ssid);
 172     void doReadPTE(Yield &yield, Addr va, Addr addr, void *ptr,
 173                    unsigned stage, unsigned level);
 174
 175   public:
 176     SMMUTranslationProcess(const std::string &name, SMMUv3 &_smmu,
 177         SMMUv3DeviceInterface &_ifc);
 178
 179     virtual ~SMMUTranslationProcess();
 180
 181     void beginTransaction(const SMMUTranslRequest &req);
 182     void resumeTransaction();
 183 };
 184
 185 #endif /* __DEV_ARM_SMMU_V3_TRANSL_HH__ */