src/dev/arm/ufs_device.cc

   1 /*
   2  * Copyright (c) 2013-2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /** @file
  39  * This is a simulation model for a UFS interface
  40  * The UFS interface consists of a host controller and (at least) one device.
  41  * The device can contain multiple logic units.
  42  * To make this interface as usefull as possible for future development, the
  43  * decision has been made to split the UFS functionality from the SCSI
  44  * functionality. The class UFS SCSIDevice can therefor be used as a starting
  45  * point for creating a more generic SCSI device. This has as a consequence
  46  * that the UFSHostDevice class contains functionality from both the host
  47  * controller and the device. The current UFS standard (1.1) allows only one
  48  * device, and up to 8 logic units. the logic units only handle the SCSI part
  49  * of the command, and the device mainly the UFS part. Yet the split between
  50  * the SCSIresume function and the SCSICMDHandle might seem a bit awkward.
  51  * The SCSICMDHandle function is in essence a SCSI reply generator, and it
  52  * distils the essential information from the command. A disktransfer cannot
  53  * be made from this position because the scatter gather list is not included
  54  * in the SCSI command, but in the Transfer Request descriptor. The device
  55  * needs to manage the data transfer. This file is build up as follows: first
  56  * the UFSSCSIDevice functions will be presented; then the UFSHostDevice
  57  * functions. The UFSHostDevice functions are split in three parts: UFS
  58  * transaction flow, data write transfer and data read transfer. The
  59  * functions are then ordered in the order in which a transfer takes place.
  60  */
  61
  62 /**
  63  * Reference material can be found at the JEDEC website:
  64  * UFS standard
  65  * http://www.jedec.org/standards-documents/results/jesd220
  66  * UFS HCI specification
  67  * http://www.jedec.org/standards-documents/results/jesd223
  68  */
  69
  70 #include "dev/arm/ufs_device.hh"
  71
  72 /**
  73  * Constructor and destructor functions of UFSHCM device
  74  */
  75 UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(const UFSHostDeviceParams &p,
  76                              uint32_t lun_id, const Callback &transfer_cb,
  77                              const Callback &read_cb):
  78     SimObject(p),
  79     flashDisk(p.image[lun_id]),
  80     flashDevice(p.internalflash[lun_id]),
  81     blkSize(p.img_blk_size),
  82     lunAvail(p.image.size()),
  83     diskSize(flashDisk->size()),
  84     capacityLower((diskSize - 1) & 0xffffffff),
  85     capacityUpper((diskSize - SectorSize) >> 32),
  86     lunID(lun_id),
  87     transferCompleted(false),
  88     readCompleted(false),
  89     totalRead(0),
  90     totalWrite(0),
  91     amountOfWriteTransfers(0),
  92     amountOfReadTransfers(0)
  93 {
  94     /**
  95      * These callbacks are used to communicate the events that are
  96      * triggered upstream; e.g. from the Memory Device to the UFS SCSI Device
  97      * or from the UFS SCSI device to the UFS host.
  98      */
  99     signalDone = transfer_cb;
 100     memReadCallback = [this]() { readCallback(); };
 101     deviceReadCallback = read_cb;
 102     memWriteCallback = [this]() { SSDWriteDone(); };
 103
 104     /**
 105      * make ascii out of lun_id (and add more characters)
 106      * UFS allows up to 8 logic units, so the numbering should work out
 107      */
 108     uint32_t temp_id = ((lun_id | 0x30) << 24) | 0x3A4449;
 109     lunInfo.dWord0 = 0x02060000;   //data
 110     lunInfo.dWord1 = 0x0200001F;
 111     lunInfo.vendor0 = 0x484D5241;  //ARMH (HMRA)
 112     lunInfo.vendor1 = 0x424D4143;  //CAMB (BMAC)
 113     lunInfo.product0 = 0x356D6567; //gem5  (5meg)
 114     lunInfo.product1 = 0x4D534655; //UFSM (MSFU)
 115     lunInfo.product2 = 0x4C45444F; //ODEL (LEDO)
 116     lunInfo.product3 = temp_id;    // ID:"lun_id" ("lun_id":DI)
 117     lunInfo.productRevision = 0x01000000; //0x01
 118
 119     DPRINTF(UFSHostDevice, "Logic unit %d assumes that %d logic units are"
 120             " present in the system\n", lunID, lunAvail);
 121     DPRINTF(UFSHostDevice,"The disksize of lun: %d should be %d blocks\n",
 122             lunID, diskSize);
 123     flashDevice->initializeMemory(diskSize, SectorSize);
 124 }
 125
 126
 127 /**
 128  * These pages are SCSI specific. For more information refer to:
 129  * Universal Flash Storage (UFS) JESD220 FEB 2011 (JEDEC)
 130  * http://www.jedec.org/standards-documents/results/jesd220
 131  */
 132 const unsigned int UFSHostDevice::UFSSCSIDevice::controlPage[3] =
 133                                                 {0x01400A0A, 0x00000000,
 134                                                  0x0000FFFF};
 135 const unsigned int UFSHostDevice::UFSSCSIDevice::recoveryPage[3] =
 136                                                 {0x03800A01, 0x00000000,
 137                                                  0xFFFF0003};
 138 const unsigned int UFSHostDevice::UFSSCSIDevice::cachingPage[5] =
 139                                                 {0x00011208, 0x00000000,
 140                                                  0x00000000, 0x00000020,
 141                                                  0x00000000};
 142
 143 UFSHostDevice::UFSSCSIDevice::~UFSSCSIDevice() {}
 144
 145 /**
 146  * UFS specific SCSI handling function.
 147  * The following attributes may still be added: SCSI format unit,
 148  * Send diagnostic and UNMAP;
 149  * Synchronize Cache and buffer read/write could not be tested yet
 150  * All parameters can be found in:
 151  * Universal Flash Storage (UFS) JESD220 FEB 2011 (JEDEC)
 152  * http://www.jedec.org/standards-documents/results/jesd220
 153  * (a JEDEC acount may be required {free of charge})
 154  */
 155
 156 struct UFSHostDevice::SCSIReply
 157 UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(uint32_t* SCSI_msg)
 158 {
 159     struct SCSIReply scsi_out;
 160     scsi_out.reset();
 161
 162     /**
 163      * Create the standard SCSI reponse information
 164      * These values might changes over the course of a transfer
 165      */
 166     scsi_out.message.header.dWord0 = UPIUHeaderDataIndWord0 |
 167         lunID << 16;
 168     scsi_out.message.header.dWord1 = UPIUHeaderDataIndWord1;
 169     scsi_out.message.header.dWord2 = UPIUHeaderDataIndWord2;
 170     statusCheck(SCSIGood, scsi_out.senseCode);
 171     scsi_out.senseSize = scsi_out.senseCode[0];
 172     scsi_out.LUN = lunID;
 173     scsi_out.status = SCSIGood;
 174
 175     DPRINTF(UFSHostDevice, "SCSI command:%2x\n", SCSI_msg[4]);
 176     /**Determine what the message is and fill the response packet*/
 177
 178     switch (SCSI_msg[4] & 0xFF) {
 179
 180       case SCSIInquiry: {
 181           /**
 182            * SCSI inquiry: tell about this specific logic unit
 183            */
 184           scsi_out.msgSize = 36;
 185           scsi_out.message.dataMsg.resize(9);
 186
 187           for (uint8_t count = 0; count < 9; count++)
 188               scsi_out.message.dataMsg[count] =
 189                   (reinterpret_cast<uint32_t*> (&lunInfo))[count];
 190       } break;
 191
 192       case SCSIRead6: {
 193           /**
 194            * Read command. Number indicates the length of the command.
 195            */
 196           scsi_out.expectMore = 0x02;
 197           scsi_out.msgSize = 0;
 198
 199           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 200
 201           /**BE and not nicely aligned. Apart from that it only has
 202            * information in five bits of the first byte that is relevant
 203            * for this field.
 204            */
 205           uint32_t tmp = *reinterpret_cast<uint32_t*>(tempptr);
 206           uint64_t read_offset = betoh(tmp) & 0x1FFFFF;
 207
 208           uint32_t read_size = tempptr[4];
 209
 210
 211           scsi_out.msgSize =  read_size * blkSize;
 212           scsi_out.offset = read_offset * blkSize;
 213
 214           if ((read_offset + read_size) > diskSize)
 215               scsi_out.status = SCSIIllegalRequest;
 216
 217           DPRINTF(UFSHostDevice, "Read6 offset: 0x%8x, for %d blocks\n",
 218                   read_offset, read_size);
 219
 220           /**
 221            * Renew status check, for the request may have been illegal
 222            */
 223           statusCheck(scsi_out.status, scsi_out.senseCode);
 224           scsi_out.senseSize = scsi_out.senseCode[0];
 225           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 226               SCSICheckCondition;
 227
 228       } break;
 229
 230       case SCSIRead10: {
 231           scsi_out.expectMore = 0x02;
 232           scsi_out.msgSize = 0;
 233
 234           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 235
 236           /**BE and not nicely aligned.*/
 237           uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
 238           uint64_t read_offset = betoh(tmp);
 239
 240           uint16_t tmpsize = *reinterpret_cast<uint16_t*>(&tempptr[7]);
 241           uint32_t read_size = betoh(tmpsize);
 242
 243           scsi_out.msgSize =  read_size * blkSize;
 244           scsi_out.offset = read_offset * blkSize;
 245
 246           if ((read_offset + read_size) > diskSize)
 247               scsi_out.status = SCSIIllegalRequest;
 248
 249           DPRINTF(UFSHostDevice, "Read10 offset: 0x%8x, for %d blocks\n",
 250                   read_offset, read_size);
 251
 252           /**
 253            * Renew status check, for the request may have been illegal
 254            */
 255           statusCheck(scsi_out.status, scsi_out.senseCode);
 256           scsi_out.senseSize = scsi_out.senseCode[0];
 257           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 258               SCSICheckCondition;
 259
 260       } break;
 261
 262       case SCSIRead16: {
 263           scsi_out.expectMore = 0x02;
 264           scsi_out.msgSize = 0;
 265
 266           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 267
 268           /**BE and not nicely aligned.*/
 269           uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
 270           uint64_t read_offset = betoh(tmp);
 271
 272           tmp = *reinterpret_cast<uint32_t*>(&tempptr[6]);
 273           read_offset = (read_offset << 32) | betoh(tmp);
 274
 275           tmp = *reinterpret_cast<uint32_t*>(&tempptr[10]);
 276           uint32_t read_size = betoh(tmp);
 277
 278           scsi_out.msgSize =  read_size * blkSize;
 279           scsi_out.offset = read_offset * blkSize;
 280
 281           if ((read_offset + read_size) > diskSize)
 282               scsi_out.status = SCSIIllegalRequest;
 283
 284           DPRINTF(UFSHostDevice, "Read16 offset: 0x%8x, for %d blocks\n",
 285                   read_offset, read_size);
 286
 287           /**
 288            * Renew status check, for the request may have been illegal
 289            */
 290           statusCheck(scsi_out.status, scsi_out.senseCode);
 291           scsi_out.senseSize = scsi_out.senseCode[0];
 292           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 293               SCSICheckCondition;
 294
 295       } break;
 296
 297       case SCSIReadCapacity10: {
 298           /**
 299            * read the capacity of the device
 300            */
 301           scsi_out.msgSize = 8;
 302           scsi_out.message.dataMsg.resize(2);
 303           scsi_out.message.dataMsg[0] =
 304               betoh(capacityLower);//last block
 305           scsi_out.message.dataMsg[1] = betoh(blkSize);//blocksize
 306
 307       } break;
 308       case SCSIReadCapacity16: {
 309           scsi_out.msgSize = 32;
 310           scsi_out.message.dataMsg.resize(8);
 311           scsi_out.message.dataMsg[0] =
 312               betoh(capacityUpper);//last block
 313           scsi_out.message.dataMsg[1] =
 314               betoh(capacityLower);//last block
 315           scsi_out.message.dataMsg[2] = betoh(blkSize);//blocksize
 316           scsi_out.message.dataMsg[3] = 0x00;//
 317           scsi_out.message.dataMsg[4] = 0x00;//reserved
 318           scsi_out.message.dataMsg[5] = 0x00;//reserved
 319           scsi_out.message.dataMsg[6] = 0x00;//reserved
 320           scsi_out.message.dataMsg[7] = 0x00;//reserved
 321
 322       } break;
 323
 324       case SCSIReportLUNs: {
 325           /**
 326            * Find out how many Logic Units this device has.
 327            */
 328           scsi_out.msgSize = (lunAvail * 8) + 8;//list + overhead
 329           scsi_out.message.dataMsg.resize(2 * lunAvail + 2);
 330           scsi_out.message.dataMsg[0] = (lunAvail * 8) << 24;//LUN listlength
 331           scsi_out.message.dataMsg[1] = 0x00;
 332
 333           for (uint8_t count = 0; count < lunAvail; count++) {
 334               //LUN "count"
 335               scsi_out.message.dataMsg[2 + 2 * count] = (count & 0x7F) << 8;
 336               scsi_out.message.dataMsg[3 + 2 * count] = 0x00;
 337           }
 338
 339       } break;
 340
 341       case SCSIStartStop: {
 342           //Just acknowledge; not deemed relevant ATM
 343           scsi_out.msgSize = 0;
 344
 345       } break;
 346
 347       case SCSITestUnitReady: {
 348           //Just acknowledge; not deemed relevant ATM
 349           scsi_out.msgSize = 0;
 350
 351       } break;
 352
 353       case SCSIVerify10: {
 354           /**
 355            * See if the blocks that the host plans to request are in range of
 356            * the device.
 357            */
 358           scsi_out.msgSize = 0;
 359
 360           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 361
 362           /**BE and not nicely aligned.*/
 363           uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
 364           uint64_t read_offset = betoh(tmp);
 365
 366           uint16_t tmpsize = *reinterpret_cast<uint16_t*>(&tempptr[7]);
 367           uint32_t read_size = betoh(tmpsize);
 368
 369           if ((read_offset + read_size) > diskSize)
 370               scsi_out.status = SCSIIllegalRequest;
 371
 372           /**
 373            * Renew status check, for the request may have been illegal
 374            */
 375           statusCheck(scsi_out.status, scsi_out.senseCode);
 376           scsi_out.senseSize = scsi_out.senseCode[0];
 377           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 378               SCSICheckCondition;
 379
 380       } break;
 381
 382       case SCSIWrite6: {
 383           /**
 384            * Write command.
 385            */
 386
 387           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 388
 389           /**BE and not nicely aligned. Apart from that it only has
 390            * information in five bits of the first byte that is relevant
 391            * for this field.
 392            */
 393           uint32_t tmp = *reinterpret_cast<uint32_t*>(tempptr);
 394           uint64_t write_offset = betoh(tmp) & 0x1FFFFF;
 395
 396           uint32_t write_size = tempptr[4];
 397
 398           scsi_out.msgSize =  write_size * blkSize;
 399           scsi_out.offset = write_offset * blkSize;
 400           scsi_out.expectMore = 0x01;
 401
 402           if ((write_offset + write_size) > diskSize)
 403               scsi_out.status = SCSIIllegalRequest;
 404
 405           DPRINTF(UFSHostDevice, "Write6 offset: 0x%8x, for %d blocks\n",
 406                   write_offset, write_size);
 407
 408           /**
 409            * Renew status check, for the request may have been illegal
 410            */
 411           statusCheck(scsi_out.status, scsi_out.senseCode);
 412           scsi_out.senseSize = scsi_out.senseCode[0];
 413           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 414               SCSICheckCondition;
 415
 416       } break;
 417
 418       case SCSIWrite10: {
 419           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 420
 421           /**BE and not nicely aligned.*/
 422           uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
 423           uint64_t write_offset = betoh(tmp);
 424
 425           uint16_t tmpsize = *reinterpret_cast<uint16_t*>(&tempptr[7]);
 426           uint32_t write_size = betoh(tmpsize);
 427
 428           scsi_out.msgSize =  write_size * blkSize;
 429           scsi_out.offset = write_offset * blkSize;
 430           scsi_out.expectMore = 0x01;
 431
 432           if ((write_offset + write_size) > diskSize)
 433               scsi_out.status = SCSIIllegalRequest;
 434
 435           DPRINTF(UFSHostDevice, "Write10 offset: 0x%8x, for %d blocks\n",
 436                   write_offset, write_size);
 437
 438           /**
 439            * Renew status check, for the request may have been illegal
 440            */
 441           statusCheck(scsi_out.status, scsi_out.senseCode);
 442           scsi_out.senseSize = scsi_out.senseCode[0];
 443           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 444               SCSICheckCondition;
 445
 446       } break;
 447
 448       case SCSIWrite16: {
 449           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 450
 451           /**BE and not nicely aligned.*/
 452           uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
 453           uint64_t write_offset = betoh(tmp);
 454
 455           tmp = *reinterpret_cast<uint32_t*>(&tempptr[6]);
 456           write_offset = (write_offset << 32) | betoh(tmp);
 457
 458           tmp = *reinterpret_cast<uint32_t*>(&tempptr[10]);
 459           uint32_t write_size = betoh(tmp);
 460
 461           scsi_out.msgSize = write_size * blkSize;
 462           scsi_out.offset = write_offset * blkSize;
 463           scsi_out.expectMore = 0x01;
 464
 465           if ((write_offset + write_size) > diskSize)
 466               scsi_out.status = SCSIIllegalRequest;
 467
 468           DPRINTF(UFSHostDevice, "Write16 offset: 0x%8x, for %d blocks\n",
 469                   write_offset, write_size);
 470
 471           /**
 472            * Renew status check, for the request may have been illegal
 473            */
 474           statusCheck(scsi_out.status, scsi_out.senseCode);
 475           scsi_out.senseSize = scsi_out.senseCode[0];
 476           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 477               SCSICheckCondition;
 478
 479       } break;
 480
 481       case SCSIFormatUnit: {//not yet verified
 482           scsi_out.msgSize = 0;
 483           scsi_out.expectMore = 0x01;
 484
 485       } break;
 486
 487       case SCSISendDiagnostic: {//not yet verified
 488           scsi_out.msgSize = 0;
 489
 490       } break;
 491
 492       case SCSISynchronizeCache: {
 493           //do we have cache (we don't have cache at this moment)
 494           //TODO: here will synchronization happen when cache is modelled
 495           scsi_out.msgSize = 0;
 496
 497       } break;
 498
 499         //UFS SCSI additional command set for full functionality
 500       case SCSIModeSelect10:
 501         //TODO:
 502         //scsi_out.expectMore = 0x01;//not supported due to modepage support
 503         //code isn't dead, code suggest what is to be done when implemented
 504         break;
 505
 506       case SCSIModeSense6: case SCSIModeSense10: {
 507           /**
 508            * Get more discriptive information about the SCSI functionality
 509            * within this logic unit.
 510            */
 511           if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x0A) {//control page
 512               scsi_out.message.dataMsg.resize((sizeof(controlPage) >> 2) + 2);
 513               scsi_out.message.dataMsg[0] = 0x00000A00;//control page code
 514               scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
 515
 516               for (uint8_t count = 0; count < 3; count++)
 517                   scsi_out.message.dataMsg[2 + count] = controlPage[count];
 518
 519               scsi_out.msgSize = 20;
 520               DPRINTF(UFSHostDevice, "CONTROL page\n");
 521
 522           } else if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x01) {//recovery page
 523               scsi_out.message.dataMsg.resize((sizeof(recoveryPage) >> 2)
 524                                               + 2);
 525
 526               scsi_out.message.dataMsg[0] = 0x00000100;//recovery page code
 527               scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
 528
 529               for (uint8_t count = 0; count < 3; count++)
 530                   scsi_out.message.dataMsg[2 + count] = recoveryPage[count];
 531
 532               scsi_out.msgSize = 20;
 533               DPRINTF(UFSHostDevice, "RECOVERY page\n");
 534
 535           } else if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x08) {//caching page
 536
 537               scsi_out.message.dataMsg.resize((sizeof(cachingPage) >> 2) + 2);
 538               scsi_out.message.dataMsg[0] = 0x00001200;//caching page code
 539               scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
 540
 541               for (uint8_t count = 0; count < 5; count++)
 542                   scsi_out.message.dataMsg[2 + count] = cachingPage[count];
 543
 544               scsi_out.msgSize = 20;
 545               DPRINTF(UFSHostDevice, "CACHE page\n");
 546
 547           } else if ((SCSI_msg[4] & 0x3F0000) >> 16 == 0x3F) {//ALL the pages!
 548
 549               scsi_out.message.dataMsg.resize(((sizeof(controlPage) +
 550                                                 sizeof(recoveryPage) +
 551                                                 sizeof(cachingPage)) >> 2)
 552                                               + 2);
 553               scsi_out.message.dataMsg[0] = 0x00003200;//all page code
 554               scsi_out.message.dataMsg[1] = 0x00000000;//See JEDEC220 ch8
 555
 556               for (uint8_t count = 0; count < 3; count++)
 557                   scsi_out.message.dataMsg[2 + count] = recoveryPage[count];
 558
 559               for (uint8_t count = 0; count < 5; count++)
 560                   scsi_out.message.dataMsg[5 + count] = cachingPage[count];
 561
 562               for (uint8_t count = 0; count < 3; count++)
 563                   scsi_out.message.dataMsg[10 + count] = controlPage[count];
 564
 565               scsi_out.msgSize = 52;
 566               DPRINTF(UFSHostDevice, "Return ALL the pages!!!\n");
 567
 568           } else inform("Wrong mode page requested\n");
 569
 570           scsi_out.message.dataCount = scsi_out.msgSize << 24;
 571       } break;
 572
 573       case SCSIRequestSense: {
 574           scsi_out.msgSize = 0;
 575
 576       } break;
 577
 578       case SCSIUnmap:break;//not yet verified
 579
 580       case SCSIWriteBuffer: {
 581           scsi_out.expectMore = 0x01;
 582
 583           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 584
 585           /**BE and not nicely aligned.*/
 586           uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
 587           uint64_t write_offset = betoh(tmp) & 0xFFFFFF;
 588
 589           tmp = *reinterpret_cast<uint32_t*>(&tempptr[5]);
 590           uint32_t write_size = betoh(tmp) & 0xFFFFFF;
 591
 592           scsi_out.msgSize =  write_size;
 593           scsi_out.offset = write_offset;
 594
 595       } break;
 596
 597       case SCSIReadBuffer: {
 598           /**
 599            * less trivial than normal read. Size is in bytes instead
 600            * of blocks, and it is assumed (though not guaranteed) that
 601            * reading is from cache.
 602            */
 603           scsi_out.expectMore = 0x02;
 604
 605           uint8_t* tempptr = reinterpret_cast<uint8_t*>(&SCSI_msg[4]);
 606
 607           /**BE and not nicely aligned.*/
 608           uint32_t tmp = *reinterpret_cast<uint32_t*>(&tempptr[2]);
 609           uint64_t read_offset = betoh(tmp) & 0xFFFFFF;
 610
 611           tmp = *reinterpret_cast<uint32_t*>(&tempptr[5]);
 612           uint32_t read_size = betoh(tmp) & 0xFFFFFF;
 613
 614           scsi_out.msgSize = read_size;
 615           scsi_out.offset = read_offset;
 616
 617           if ((read_offset + read_size) > capacityLower * blkSize)
 618               scsi_out.status = SCSIIllegalRequest;
 619
 620           DPRINTF(UFSHostDevice, "Read buffer location: 0x%8x\n",
 621                   read_offset);
 622           DPRINTF(UFSHostDevice, "Number of bytes: 0x%8x\n", read_size);
 623
 624           statusCheck(scsi_out.status, scsi_out.senseCode);
 625           scsi_out.senseSize = scsi_out.senseCode[0];
 626           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 627               SCSICheckCondition;
 628
 629       } break;
 630
 631       case SCSIMaintenanceIn: {
 632           /**
 633            * linux sends this command three times from kernel 3.9 onwards,
 634            * UFS does not support it, nor does this model. Linux knows this,
 635            * but tries anyway (useful for some SD card types).
 636            * Lets make clear we don't want it and just ignore it.
 637            */
 638           DPRINTF(UFSHostDevice, "Ignoring Maintenance In command\n");
 639           statusCheck(SCSIIllegalRequest, scsi_out.senseCode);
 640           scsi_out.senseSize = scsi_out.senseCode[0];
 641           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 642               SCSICheckCondition;
 643           scsi_out.msgSize = 0;
 644       } break;
 645
 646       default: {
 647           statusCheck(SCSIIllegalRequest, scsi_out.senseCode);
 648           scsi_out.senseSize = scsi_out.senseCode[0];
 649           scsi_out.status = (scsi_out.status == SCSIGood) ? SCSIGood :
 650               SCSICheckCondition;
 651           scsi_out.msgSize = 0;
 652           inform("Unsupported scsi message type: %2x\n", SCSI_msg[4] & 0xFF);
 653           inform("0x%8x\n", SCSI_msg[0]);
 654           inform("0x%8x\n", SCSI_msg[1]);
 655           inform("0x%8x\n", SCSI_msg[2]);
 656           inform("0x%8x\n", SCSI_msg[3]);
 657           inform("0x%8x\n", SCSI_msg[4]);
 658       } break;
 659     }
 660
 661     return scsi_out;
 662 }
 663
 664 /**
 665  * SCSI status check function. generic device test, creates sense codes
 666  * Future versions may include TODO: device checks, which is why this is
 667  * in a separate function.
 668  */
 669
 670 void
 671 UFSHostDevice::UFSSCSIDevice::statusCheck(uint8_t status,
 672                                 uint8_t* sensecodelist)
 673 {
 674     for (uint8_t count = 0; count < 19; count++)
 675         sensecodelist[count] = 0;
 676
 677     sensecodelist[0] = 18; //sense length
 678     sensecodelist[1] = 0x70; //we send a valid frame
 679     sensecodelist[3] = status & 0xF; //mask to be sure + sensecode
 680     sensecodelist[8] = 0x1F; //data length
 681 }
 682
 683 /**
 684  * read from the flashdisk
 685  */
 686
 687 void
 688 UFSHostDevice::UFSSCSIDevice::readFlash(uint8_t* readaddr, uint64_t offset,
 689                                    uint32_t size)
 690 {
 691     /** read from image, and get to memory */
 692     for (int count = 0; count < (size / SectorSize); count++)
 693         flashDisk->read(&(readaddr[SectorSize*count]), (offset /
 694                                                         SectorSize) + count);
 695 }
 696
 697 /**
 698  * Write to the flashdisk
 699  */
 700
 701 void
 702 UFSHostDevice::UFSSCSIDevice::writeFlash(uint8_t* writeaddr, uint64_t offset,
 703                                     uint32_t size)
 704 {
 705     /** Get from fifo and write to image*/
 706     for (int count = 0; count < (size / SectorSize); count++)
 707         flashDisk->write(&(writeaddr[SectorSize * count]),
 708                          (offset / SectorSize) + count);
 709 }
 710
 711 /**
 712  * Constructor for the UFS Host device
 713  */
 714
 715 UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams &p) :
 716     DmaDevice(p),
 717     pioAddr(p.pio_addr),
 718     pioSize(0x0FFF),
 719     pioDelay(p.pio_latency),
 720     intNum(p.int_num),
 721     gic(p.gic),
 722     lunAvail(p.image.size()),
 723     UFSSlots(p.ufs_slots - 1),
 724     readPendingNum(0),
 725     writePendingNum(0),
 726     activeDoorbells(0),
 727     pendingDoorbells(0),
 728     countInt(0),
 729     transferTrack(0),
 730     taskCommandTrack(0),
 731     idlePhaseStart(0),
 732     stats(this),
 733     SCSIResumeEvent([this]{ SCSIStart(); }, name()),
 734     UTPEvent([this]{ finalUTP(); }, name())
 735 {
 736     DPRINTF(UFSHostDevice, "The hostcontroller hosts %d Logic units\n",
 737             lunAvail);
 738     UFSDevice.resize(lunAvail);
 739
 740     for (int count = 0; count < lunAvail; count++) {
 741         UFSDevice[count] = new UFSSCSIDevice(p, count,
 742                 [this]() { LUNSignal(); },
 743                 [this]() { readCallback(); });
 744     }
 745
 746     if (UFSSlots > 31)
 747         warn("UFSSlots = %d, this will results in %d command slots",
 748              UFSSlots, (UFSSlots & 0x1F));
 749
 750     if ((UFSSlots & 0x1F) == 0)
 751         fatal("Number of UFS command slots should be between 1 and 32.");
 752
 753     setValues();
 754 }
 755
 756 UFSHostDevice::
 757 UFSHostDeviceStats::UFSHostDeviceStats(UFSHostDevice *parent)
 758     : Stats::Group(parent, "UFSDiskHost"),
 759       ADD_STAT(currentSCSIQueue,
 760                "Most up to date length of the command queue"),
 761       ADD_STAT(currentReadSSDQueue,
 762                "Most up to date length of the read SSD queue"),
 763       ADD_STAT(currentWriteSSDQueue,
 764                "Most up to date length of the write SSD queue"),
 765       /** Amount of data read/written */
 766       ADD_STAT(totalReadSSD, "Number of bytes read from SSD"),
 767       ADD_STAT(totalWrittenSSD, "Number of bytes written to SSD"),
 768       ADD_STAT(totalReadDiskTransactions,"Number of transactions from disk"),
 769       ADD_STAT(totalWriteDiskTransactions, "Number of transactions to disk"),
 770       ADD_STAT(totalReadUFSTransactions, "Number of transactions from device"),
 771       ADD_STAT(totalWriteUFSTransactions, "Number of transactions to device"),
 772       /** Average bandwidth for reads and writes */
 773       ADD_STAT(averageReadSSDBW, "Average read bandwidth (bytes/s)",
 774                totalReadSSD / simSeconds),
 775       ADD_STAT(averageWriteSSDBW, "Average write bandwidth (bytes/s)",
 776                totalWrittenSSD / simSeconds),
 777       ADD_STAT(averageSCSIQueue, "Average command queue length"),
 778       ADD_STAT(averageReadSSDQueue, "Average read queue length"),
 779       ADD_STAT(averageWriteSSDQueue, "Average write queue length"),
 780       /** Number of doorbells rung*/
 781       ADD_STAT(curDoorbell, "Most up to date number of doorbells used",
 782                parent->activeDoorbells),
 783       ADD_STAT(maxDoorbell, "Maximum number of doorbells utilized"),
 784       ADD_STAT(averageDoorbell, "Average number of Doorbells used"),
 785       /** Latency*/
 786       ADD_STAT(transactionLatency, "Histogram of transaction times"),
 787       ADD_STAT(idleTimes, "Histogram of idle times")
 788 {
 789     using namespace Stats;
 790
 791     // Register the stats
 792     /** Queue lengths */
 793     currentSCSIQueue
 794         .flags(none);
 795     currentReadSSDQueue
 796         .flags(none);
 797     currentWriteSSDQueue
 798         .flags(none);
 799
 800     /** Amount of data read/written */
 801     totalReadSSD
 802         .flags(none);
 803
 804     totalWrittenSSD
 805         .flags(none);
 806
 807     totalReadDiskTransactions
 808         .flags(none);
 809     totalWriteDiskTransactions
 810         .flags(none);
 811     totalReadUFSTransactions
 812         .flags(none);
 813     totalWriteUFSTransactions
 814         .flags(none);
 815
 816     /** Average bandwidth for reads and writes */
 817     averageReadSSDBW
 818         .flags(nozero);
 819
 820     averageWriteSSDBW
 821         .flags(nozero);
 822
 823     averageSCSIQueue
 824         .flags(nozero);
 825     averageReadSSDQueue
 826         .flags(nozero);
 827     averageWriteSSDQueue
 828         .flags(nozero);
 829
 830     /** Number of doorbells rung*/
 831     curDoorbell
 832         .flags(none);
 833
 834     maxDoorbell
 835         .flags(none);
 836     averageDoorbell
 837         .flags(nozero);
 838
 839     /** Latency*/
 840     transactionLatency
 841         .init(100)
 842         .flags(pdf);
 843
 844     idleTimes
 845         .init(100)
 846         .flags(pdf);
 847 }
 848
 849 /**
 850  * Register init
 851  */
 852 void UFSHostDevice::setValues()
 853 {
 854     /**
 855      * The capability register is built up as follows:
 856      * 31-29 RES; Testmode support; O3 delivery; 64 bit addr;
 857      * 23-19 RES; 18-16 #TM Req slots; 15-5 RES;4-0 # TR slots
 858      */
 859     UFSHCIMem.HCCAP = 0x06070000 | (UFSSlots & 0x1F);
 860     UFSHCIMem.HCversion = 0x00010000; //version is 1.0
 861     UFSHCIMem.HCHCDDID = 0xAA003C3C;// Arbitrary number
 862     UFSHCIMem.HCHCPMID = 0x41524D48; //ARMH (not an official MIPI number)
 863     UFSHCIMem.TRUTRLDBR = 0x00;
 864     UFSHCIMem.TMUTMRLDBR = 0x00;
 865     UFSHCIMem.CMDUICCMDR = 0x00;
 866     // We can process CMD, TM, TR, device present
 867     UFSHCIMem.ORHostControllerStatus = 0x08;
 868     UFSHCIMem.TRUTRLBA = 0x00;
 869     UFSHCIMem.TRUTRLBAU = 0x00;
 870     UFSHCIMem.TMUTMRLBA = 0x00;
 871     UFSHCIMem.TMUTMRLBAU = 0x00;
 872 }
 873
 874 /**
 875  * Determine address ranges
 876  */
 877
 878 AddrRangeList
 879 UFSHostDevice::getAddrRanges() const
 880 {
 881     AddrRangeList ranges;
 882     ranges.push_back(RangeSize(pioAddr, pioSize));
 883     return ranges;
 884 }
 885
 886 /**
 887  * UFSHCD read register. This function allows the system to read the
 888  * register entries
 889  */
 890
 891 Tick
 892 UFSHostDevice::read(PacketPtr pkt)
 893 {
 894     uint32_t data = 0;
 895
 896     switch (pkt->getAddr() & 0xFF)
 897     {
 898
 899       case regControllerCapabilities:
 900         data = UFSHCIMem.HCCAP;
 901         break;
 902
 903       case regUFSVersion:
 904         data = UFSHCIMem.HCversion;
 905         break;
 906
 907       case regControllerDEVID:
 908         data = UFSHCIMem.HCHCDDID;
 909         break;
 910
 911       case regControllerPRODID:
 912         data = UFSHCIMem.HCHCPMID;
 913         break;
 914
 915       case regInterruptStatus:
 916         data = UFSHCIMem.ORInterruptStatus;
 917         UFSHCIMem.ORInterruptStatus = 0x00;
 918         //TODO: Revise and extend
 919         clearInterrupt();
 920         break;
 921
 922       case regInterruptEnable:
 923         data = UFSHCIMem.ORInterruptEnable;
 924         break;
 925
 926       case regControllerStatus:
 927         data = UFSHCIMem.ORHostControllerStatus;
 928         break;
 929
 930       case regControllerEnable:
 931         data = UFSHCIMem.ORHostControllerEnable;
 932         break;
 933
 934       case regUICErrorCodePHYAdapterLayer:
 935         data = UFSHCIMem.ORUECPA;
 936         break;
 937
 938       case regUICErrorCodeDataLinkLayer:
 939         data = UFSHCIMem.ORUECDL;
 940         break;
 941
 942       case regUICErrorCodeNetworkLayer:
 943         data = UFSHCIMem.ORUECN;
 944         break;
 945
 946       case regUICErrorCodeTransportLayer:
 947         data = UFSHCIMem.ORUECT;
 948         break;
 949
 950       case regUICErrorCodeDME:
 951         data = UFSHCIMem.ORUECDME;
 952         break;
 953
 954       case regUTPTransferREQINTAGGControl:
 955         data = UFSHCIMem.ORUTRIACR;
 956         break;
 957
 958       case regUTPTransferREQListBaseL:
 959         data = UFSHCIMem.TRUTRLBA;
 960         break;
 961
 962       case regUTPTransferREQListBaseH:
 963         data = UFSHCIMem.TRUTRLBAU;
 964         break;
 965
 966       case regUTPTransferREQDoorbell:
 967         data = UFSHCIMem.TRUTRLDBR;
 968         break;
 969
 970       case regUTPTransferREQListClear:
 971         data = UFSHCIMem.TRUTRLCLR;
 972         break;
 973
 974       case regUTPTransferREQListRunStop:
 975         data = UFSHCIMem.TRUTRLRSR;
 976         break;
 977
 978       case regUTPTaskREQListBaseL:
 979         data = UFSHCIMem.TMUTMRLBA;
 980         break;
 981
 982       case regUTPTaskREQListBaseH:
 983         data = UFSHCIMem.TMUTMRLBAU;
 984         break;
 985
 986       case regUTPTaskREQDoorbell:
 987         data = UFSHCIMem.TMUTMRLDBR;
 988         break;
 989
 990       case regUTPTaskREQListClear:
 991         data = UFSHCIMem.TMUTMRLCLR;
 992         break;
 993
 994       case regUTPTaskREQListRunStop:
 995         data = UFSHCIMem.TMUTMRLRSR;
 996         break;
 997
 998       case regUICCommand:
 999         data = UFSHCIMem.CMDUICCMDR;
1000         break;
1001
1002       case regUICCommandArg1:
1003         data = UFSHCIMem.CMDUCMDARG1;
1004         break;
1005
1006       case regUICCommandArg2:
1007         data = UFSHCIMem.CMDUCMDARG2;
1008         break;
1009
1010       case regUICCommandArg3:
1011         data = UFSHCIMem.CMDUCMDARG3;
1012         break;
1013
1014       default:
1015         data = 0x00;
1016         break;
1017     }
1018
1019     pkt->setLE<uint32_t>(data);
1020     pkt->makeResponse();
1021     return pioDelay;
1022 }
1023
1024 /**
1025  * UFSHCD write function. This function allows access to the writeable
1026  * registers. If any function attempts to write value to an unwriteable
1027  * register entry, then the value will not be written.
1028  */
1029 Tick
1030 UFSHostDevice::write(PacketPtr pkt)
1031 {
1032     uint32_t data = 0;
1033
1034     switch (pkt->getSize()) {
1035
1036       case 1:
1037         data = pkt->getLE<uint8_t>();
1038         break;
1039
1040       case 2:
1041         data = pkt->getLE<uint16_t>();
1042         break;
1043
1044       case 4:
1045         data = pkt->getLE<uint32_t>();
1046         break;
1047
1048       default:
1049         panic("Undefined UFSHCD controller write size!\n");
1050         break;
1051     }
1052
1053     switch (pkt->getAddr() & 0xFF)
1054     {
1055       case regControllerCapabilities://you shall not write to this
1056         break;
1057
1058       case regUFSVersion://you shall not write to this
1059         break;
1060
1061       case regControllerDEVID://you shall not write to this
1062         break;
1063
1064       case regControllerPRODID://you shall not write to this
1065         break;
1066
1067       case regInterruptStatus://you shall not write to this
1068         break;
1069
1070       case regInterruptEnable:
1071         UFSHCIMem.ORInterruptEnable = data;
1072         break;
1073
1074       case regControllerStatus:
1075         UFSHCIMem.ORHostControllerStatus = data;
1076         break;
1077
1078       case regControllerEnable:
1079         UFSHCIMem.ORHostControllerEnable = data;
1080         break;
1081
1082       case regUICErrorCodePHYAdapterLayer:
1083         UFSHCIMem.ORUECPA = data;
1084         break;
1085
1086       case regUICErrorCodeDataLinkLayer:
1087         UFSHCIMem.ORUECDL = data;
1088         break;
1089
1090       case regUICErrorCodeNetworkLayer:
1091         UFSHCIMem.ORUECN = data;
1092         break;
1093
1094       case regUICErrorCodeTransportLayer:
1095         UFSHCIMem.ORUECT = data;
1096         break;
1097
1098       case regUICErrorCodeDME:
1099         UFSHCIMem.ORUECDME = data;
1100         break;
1101
1102       case regUTPTransferREQINTAGGControl:
1103         UFSHCIMem.ORUTRIACR = data;
1104         break;
1105
1106       case regUTPTransferREQListBaseL:
1107         UFSHCIMem.TRUTRLBA = data;
1108         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1109             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU)!= 0x00))
1110             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1111         break;
1112
1113       case regUTPTransferREQListBaseH:
1114         UFSHCIMem.TRUTRLBAU = data;
1115         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1116             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1117             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1118         break;
1119
1120       case regUTPTransferREQDoorbell:
1121         if (!(UFSHCIMem.TRUTRLDBR) && data)
1122             stats.idleTimes.sample(curTick() - idlePhaseStart);
1123         UFSHCIMem.TRUTRLDBR |= data;
1124         requestHandler();
1125         break;
1126
1127       case regUTPTransferREQListClear:
1128         UFSHCIMem.TRUTRLCLR = data;
1129         break;
1130
1131       case regUTPTransferREQListRunStop:
1132         UFSHCIMem.TRUTRLRSR = data;
1133         break;
1134
1135       case regUTPTaskREQListBaseL:
1136         UFSHCIMem.TMUTMRLBA = data;
1137         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1138             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1139             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1140         break;
1141
1142       case regUTPTaskREQListBaseH:
1143         UFSHCIMem.TMUTMRLBAU = data;
1144         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1145             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1146             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1147         break;
1148
1149       case regUTPTaskREQDoorbell:
1150         UFSHCIMem.TMUTMRLDBR |= data;
1151         requestHandler();
1152         break;
1153
1154       case regUTPTaskREQListClear:
1155         UFSHCIMem.TMUTMRLCLR = data;
1156         break;
1157
1158       case regUTPTaskREQListRunStop:
1159         UFSHCIMem.TMUTMRLRSR = data;
1160         break;
1161
1162       case regUICCommand:
1163         UFSHCIMem.CMDUICCMDR = data;
1164         requestHandler();
1165         break;
1166
1167       case regUICCommandArg1:
1168         UFSHCIMem.CMDUCMDARG1 = data;
1169         break;
1170
1171       case regUICCommandArg2:
1172         UFSHCIMem.CMDUCMDARG2 = data;
1173         break;
1174
1175       case regUICCommandArg3:
1176         UFSHCIMem.CMDUCMDARG3 = data;
1177         break;
1178
1179       default:break;//nothing happens, you try to access a register that
1180                     //does not exist
1181
1182     }
1183
1184     pkt->makeResponse();
1185     return pioDelay;
1186 }
1187
1188 /**
1189  * Request handler. Determines where the request comes from and initiates the
1190  * appropriate actions accordingly.
1191  */
1192
1193 void
1194 UFSHostDevice::requestHandler()
1195 {
1196     Addr address = 0x00;
1197     int mask = 0x01;
1198     int size;
1199     int count = 0;
1200     struct taskStart task_info;
1201     struct transferStart transferstart_info;
1202     transferstart_info.done = 0;
1203
1204     /**
1205      * step1 determine what called us
1206      * step2 determine where to get it
1207      * Look for any request of which we where not yet aware
1208      */
1209     while (((UFSHCIMem.CMDUICCMDR > 0x00) |
1210             ((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack) > 0x00) |
1211             ((UFSHCIMem.TRUTRLDBR ^ transferTrack) > 0x00)) ) {
1212
1213         if (UFSHCIMem.CMDUICCMDR > 0x00) {
1214             /**
1215              * Command; general control of the Host controller.
1216              * no DMA transfer needed
1217              */
1218             commandHandler();
1219             UFSHCIMem.ORInterruptStatus |= UICCommandCOMPL;
1220             generateInterrupt();
1221             UFSHCIMem.CMDUICCMDR = 0x00;
1222             return; //command, nothing more we can do
1223
1224         } else if ((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack) > 0x00) {
1225             /**
1226              * Task; flow control, meant for the device/Logic unit
1227              * DMA transfer is needed, flash will not be approached
1228              */
1229             size = sizeof(UTPUPIUTaskReq);
1230             /**Find the position that is not handled yet*/
1231             count = findLsbSet((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack));
1232             address = UFSHCIMem.TMUTMRLBAU;
1233             //<-64 bit
1234             address = (count * size) + (address << 32) +
1235                 UFSHCIMem.TMUTMRLBA;
1236             taskCommandTrack |= mask << count;
1237
1238             inform("UFSmodel received a task from the system; this might"
1239                    " lead to untested behaviour.\n");
1240
1241             task_info.mask = mask << count;
1242             task_info.address = address;
1243             task_info.size = size;
1244             task_info.done = UFSHCIMem.TMUTMRLDBR;
1245             taskInfo.push_back(task_info);
1246             taskEventQueue.push_back(
1247                 EventFunctionWrapper([this]{ taskStart(); }, name()));
1248             writeDevice(&taskEventQueue.back(), false, address, size,
1249                         reinterpret_cast<uint8_t*>
1250                         (&taskInfo.back().destination), 0, 0);
1251
1252         } else if ((UFSHCIMem.TRUTRLDBR ^ transferTrack) > 0x00) {
1253             /**
1254              * Transfer; Data transfer from or to the disk. There will be DMA
1255              * transfers, and the flash might be approached. Further
1256              * commands, are needed to specify the exact command.
1257              */
1258             size = sizeof(UTPTransferReqDesc);
1259             /**Find the position that is not handled yet*/
1260             count = findLsbSet((UFSHCIMem.TRUTRLDBR ^ transferTrack));
1261             address = UFSHCIMem.TRUTRLBAU;
1262             //<-64 bit
1263             address = (count * size) + (address << 32) + UFSHCIMem.TRUTRLBA;
1264
1265             transferTrack |= mask << count;
1266             DPRINTF(UFSHostDevice, "Doorbell register: 0x%8x select #:"
1267                     " 0x%8x completion info: 0x%8x\n", UFSHCIMem.TRUTRLDBR,
1268                     count, transferstart_info.done);
1269
1270             transferstart_info.done = UFSHCIMem.TRUTRLDBR;
1271
1272             /**stats**/
1273             transactionStart[count] = curTick(); //note the start time
1274             ++activeDoorbells;
1275             stats.maxDoorbell = (stats.maxDoorbell.value() < activeDoorbells)
1276                 ? activeDoorbells : stats.maxDoorbell.value();
1277             stats.averageDoorbell = stats.maxDoorbell.value();
1278
1279             /**
1280              * step3 start transfer
1281              * step4 register information; allowing the host to respond in
1282              * the end
1283              */
1284             transferstart_info.mask = mask << count;
1285             transferstart_info.address = address;
1286             transferstart_info.size = size;
1287             transferstart_info.done = UFSHCIMem.TRUTRLDBR;
1288             transferStartInfo.push_back(transferstart_info);
1289
1290             /**Deleted in readDone, queued in finalUTP*/
1291             transferStartInfo.back().destination = new struct
1292                 UTPTransferReqDesc;
1293             DPRINTF(UFSHostDevice, "Initial transfer start: 0x%8x\n",
1294                     transferstart_info.done);
1295             transferEventQueue.push_back(
1296                 EventFunctionWrapper([this]{ transferStart(); }, name()));
1297
1298             if (transferEventQueue.size() < 2) {
1299                 writeDevice(&transferEventQueue.front(), false,
1300                             address, size, reinterpret_cast<uint8_t*>
1301                             (transferStartInfo.front().destination),0, 0);
1302                 DPRINTF(UFSHostDevice, "Transfer scheduled\n");
1303             }
1304         }
1305     }
1306 }
1307
1308 /**
1309  * Task start event
1310  */
1311
1312 void
1313 UFSHostDevice::taskStart()
1314 {
1315     DPRINTF(UFSHostDevice, "Task start");
1316     taskHandler(&taskInfo.front().destination, taskInfo.front().mask,
1317                 taskInfo.front().address, taskInfo.front().size);
1318     taskInfo.pop_front();
1319     taskEventQueue.pop_front();
1320 }
1321
1322 /**
1323  * Transfer start event
1324  */
1325
1326 void
1327 UFSHostDevice::transferStart()
1328 {
1329     DPRINTF(UFSHostDevice, "Enter transfer event\n");
1330     transferHandler(transferStartInfo.front().destination,
1331                     transferStartInfo.front().mask,
1332                     transferStartInfo.front().address,
1333                     transferStartInfo.front().size,
1334                     transferStartInfo.front().done);
1335
1336     transferStartInfo.pop_front();
1337     DPRINTF(UFSHostDevice, "Transfer queue size at end of event: "
1338             "0x%8x\n", transferEventQueue.size());
1339 }
1340
1341 /**
1342  * Handles the commands that are given. At this point in time, not many
1343  * commands have been implemented in the driver.
1344  */
1345
1346 void
1347 UFSHostDevice::commandHandler()
1348 {
1349     if (UFSHCIMem.CMDUICCMDR == 0x16) {
1350         UFSHCIMem.ORHostControllerStatus |= 0x0F;//link startup
1351     }
1352
1353 }
1354
1355 /**
1356  * Handles the tasks that are given. At this point in time, not many tasks
1357  * have been implemented in the driver.
1358  */
1359
1360 void
1361 UFSHostDevice::taskHandler(struct UTPUPIUTaskReq* request_in,
1362                            uint32_t req_pos, Addr finaladdress, uint32_t
1363                            finalsize)
1364 {
1365     /**
1366      * For now, just unpack and acknowledge the task without doing anything.
1367      * TODO Implement UFS tasks.
1368      */
1369     inform("taskHandler\n");
1370     inform("%8x\n", request_in->header.dWord0);
1371     inform("%8x\n", request_in->header.dWord1);
1372     inform("%8x\n", request_in->header.dWord2);
1373
1374     request_in->header.dWord2 &= 0xffffff00;
1375
1376     UFSHCIMem.TMUTMRLDBR &= ~(req_pos);
1377     taskCommandTrack &= ~(req_pos);
1378     UFSHCIMem.ORInterruptStatus |= UTPTaskREQCOMPL;
1379
1380     readDevice(true, finaladdress, finalsize, reinterpret_cast<uint8_t*>
1381                (request_in), true, NULL);
1382
1383 }
1384
1385 /**
1386  * Obtains the SCSI command (if any)
1387  * Two possibilities: if it contains a SCSI command, then it is a usable
1388  * message; if it doesnt contain a SCSI message, then it can't be handeld
1389  * by this code.
1390  * This is the second stage of the transfer. We have the information about
1391  * where the next command can be found and what the type of command is. The
1392  * actions that are needed from the device its side are: get the information
1393  * and store the information such that we can reply.
1394  */
1395
1396 void
1397 UFSHostDevice::transferHandler(struct UTPTransferReqDesc* request_in,
1398                                int req_pos, Addr finaladdress, uint32_t
1399                                finalsize, uint32_t done)
1400 {
1401
1402     Addr cmd_desc_addr = 0x00;
1403
1404
1405     //acknowledge handling of the message
1406     DPRINTF(UFSHostDevice, "SCSI message detected\n");
1407     request_in->header.dWord2 &= 0xffffff00;
1408     SCSIInfo.RequestIn = request_in;
1409     SCSIInfo.reqPos = req_pos;
1410     SCSIInfo.finalAddress = finaladdress;
1411     SCSIInfo.finalSize = finalsize;
1412     SCSIInfo.destination.resize(request_in->PRDTableOffset * 4
1413         + request_in->PRDTableLength * sizeof(UFSHCDSGEntry));
1414     SCSIInfo.done = done;
1415
1416     assert(!SCSIResumeEvent.scheduled());
1417     /**
1418      *Get the UTP command that has the SCSI command
1419      */
1420     cmd_desc_addr = request_in->commandDescBaseAddrHi;
1421     cmd_desc_addr = (cmd_desc_addr << 32) |
1422         (request_in->commandDescBaseAddrLo & 0xffffffff);
1423
1424     writeDevice(&SCSIResumeEvent, false, cmd_desc_addr,
1425                 SCSIInfo.destination.size(), &SCSIInfo.destination[0],0, 0);
1426
1427     DPRINTF(UFSHostDevice, "SCSI scheduled\n");
1428
1429     transferEventQueue.pop_front();
1430 }
1431
1432 /**
1433  * Obtain LUN and put it in the right LUN queue. Each LUN has its own queue
1434  * of commands that need to be executed. This is the first instance where it
1435  * can be determined which Logic unit should handle the transfer. Then check
1436  * wether it should wait and queue or if it can continue.
1437  */
1438
1439 void
1440 UFSHostDevice::SCSIStart()
1441 {
1442     DPRINTF(UFSHostDevice, "SCSI message on hold until ready\n");
1443     uint32_t LUN = SCSIInfo.destination[2];
1444     UFSDevice[LUN]->SCSIInfoQueue.push_back(SCSIInfo);
1445
1446     DPRINTF(UFSHostDevice, "SCSI queue %d has %d elements\n", LUN,
1447             UFSDevice[LUN]->SCSIInfoQueue.size());
1448
1449     /**There are 32 doorbells, so at max there can be 32 transactions*/
1450     if (UFSDevice[LUN]->SCSIInfoQueue.size() < 2) //LUN is available
1451         SCSIResume(LUN);
1452
1453     else if (UFSDevice[LUN]->SCSIInfoQueue.size() > 32)
1454         panic("SCSI queue is getting too big %d\n", UFSDevice[LUN]->
1455               SCSIInfoQueue.size());
1456
1457     /**
1458      * First transfer is done, fetch the next;
1459      * At this point, the device is busy, not the HC
1460      */
1461     if (!transferEventQueue.empty()) {
1462
1463         /**
1464          * loading next data packet in case Another LUN
1465          * is approached in the mean time
1466          */
1467         writeDevice(&transferEventQueue.front(), false,
1468                     transferStartInfo.front().address,
1469                     transferStartInfo.front().size, reinterpret_cast<uint8_t*>
1470                     (transferStartInfo.front().destination), 0, 0);
1471
1472         DPRINTF(UFSHostDevice, "Transfer scheduled");
1473     }
1474 }
1475
1476 /**
1477  * Handles the transfer requests that are given.
1478  * There can be three types of transfer. SCSI specific, Reads and writes
1479  * apart from the data transfer, this also generates its own reply (UPIU
1480  * response). Information for this reply is stored in transferInfo and will
1481  * be used in transferDone
1482  */
1483
1484 void
1485 UFSHostDevice::SCSIResume(uint32_t lun_id)
1486 {
1487     DPRINTF(UFSHostDevice, "SCSIresume\n");
1488     if (UFSDevice[lun_id]->SCSIInfoQueue.empty())
1489         panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id,
1490               UFSHCIMem.TRUTRLDBR);
1491
1492     /**old info, lets form it such that we can understand it*/
1493     struct UTPTransferReqDesc* request_in = UFSDevice[lun_id]->
1494         SCSIInfoQueue.front().RequestIn;
1495
1496     uint32_t req_pos = UFSDevice[lun_id]->SCSIInfoQueue.front().reqPos;
1497
1498     Addr finaladdress = UFSDevice[lun_id]->SCSIInfoQueue.front().
1499         finalAddress;
1500
1501     uint32_t finalsize = UFSDevice[lun_id]->SCSIInfoQueue.front().finalSize;
1502
1503     uint32_t* transfercommand = reinterpret_cast<uint32_t*>
1504         (&(UFSDevice[lun_id]->SCSIInfoQueue.front().destination[0]));
1505
1506     DPRINTF(UFSHostDevice, "Task tag: 0x%8x\n", transfercommand[0]>>24);
1507     /**call logic unit to handle SCSI command*/
1508     request_out_datain = UFSDevice[(transfercommand[0] & 0xFF0000) >> 16]->
1509         SCSICMDHandle(transfercommand);
1510
1511     DPRINTF(UFSHostDevice, "LUN: %d\n", request_out_datain.LUN);
1512
1513     /**
1514      * build response stating that it was succesful
1515      * command completion, Logic unit number, and Task tag
1516      */
1517     request_in->header.dWord0 = ((request_in->header.dWord0 >> 24) == 0x21)
1518         ? 0x36 : 0x21;
1519     UFSDevice[lun_id]->transferInfo.requestOut.header.dWord0 =
1520         request_in->header.dWord0 | (request_out_datain.LUN << 8)
1521         | (transfercommand[0] & 0xFF000000);
1522     /**SCSI status reply*/
1523     UFSDevice[lun_id]->transferInfo.requestOut.header.dWord1 = 0x00000000 |
1524         (request_out_datain.status << 24);
1525     /**segment size + EHS length (see UFS standard ch7)*/
1526     UFSDevice[lun_id]->transferInfo.requestOut.header.dWord2 = 0x00000000 |
1527         ((request_out_datain.senseSize + 2) << 24) | 0x05;
1528     /**amount of data that will follow*/
1529     UFSDevice[lun_id]->transferInfo.requestOut.senseDataLen =
1530         request_out_datain.senseSize;
1531
1532     //data
1533     for (uint8_t count = 0; count<request_out_datain.senseSize; count++) {
1534         UFSDevice[lun_id]->transferInfo.requestOut.senseData[count] =
1535             request_out_datain.senseCode[count + 1];
1536     }
1537
1538     /*
1539      * At position defined by "request_in->PRDTableOffset" (counting 32 bit
1540      * words) in array "transfercommand" we have a scatter gather list, which
1541      * is usefull to us if we interpreted it as a UFSHCDSGEntry structure.
1542      */
1543     struct UFSHCDSGEntry* sglist =  reinterpret_cast<UFSHCDSGEntry*>
1544         (&(transfercommand[(request_in->PRDTableOffset)]));
1545
1546     uint32_t length = request_in->PRDTableLength;
1547     DPRINTF(UFSHostDevice, "# PRDT entries: %d\n", length);
1548
1549     Addr response_addr = request_in->commandDescBaseAddrHi;
1550     response_addr = (response_addr << 32) |
1551         ((request_in->commandDescBaseAddrLo +
1552           (request_in->responseUPIULength << 2)) & 0xffffffff);
1553
1554     /**transferdone information packet filling*/
1555     UFSDevice[lun_id]->transferInfo.responseStartAddr = response_addr;
1556     UFSDevice[lun_id]->transferInfo.reqPos = req_pos;
1557     UFSDevice[lun_id]->transferInfo.size = finalsize;
1558     UFSDevice[lun_id]->transferInfo.address = finaladdress;
1559     UFSDevice[lun_id]->transferInfo.destination = reinterpret_cast<uint8_t*>
1560         (UFSDevice[lun_id]->SCSIInfoQueue.front().RequestIn);
1561     UFSDevice[lun_id]->transferInfo.finished = true;
1562     UFSDevice[lun_id]->transferInfo.lunID = request_out_datain.LUN;
1563
1564     /**
1565      * In this part the data that needs to be transfered will be initiated
1566      * and the chain of DMA (and potentially) disk transactions will be
1567      * started.
1568      */
1569     if (request_out_datain.expectMore == 0x01) {
1570         /**write transfer*/
1571         manageWriteTransfer(request_out_datain.LUN, request_out_datain.offset,
1572                             length, sglist);
1573
1574     } else if (request_out_datain.expectMore == 0x02) {
1575         /**read transfer*/
1576         manageReadTransfer(request_out_datain.msgSize, request_out_datain.LUN,
1577                            request_out_datain.offset, length, sglist);
1578
1579     } else {
1580         /**not disk related transfer, SCSI maintanance*/
1581         uint32_t count = 0;
1582         uint32_t size_accum = 0;
1583         DPRINTF(UFSHostDevice, "Data DMA size: 0x%8x\n",
1584                 request_out_datain.msgSize);
1585
1586         /**Transport the SCSI reponse data according to the SG list*/
1587         while ((length > count) && size_accum
1588                < (request_out_datain.msgSize - 1) &&
1589                (request_out_datain.msgSize != 0x00)) {
1590             Addr SCSI_start = sglist[count].upperAddr;
1591             SCSI_start = (SCSI_start << 32) |
1592                 (sglist[count].baseAddr & 0xFFFFFFFF);
1593             DPRINTF(UFSHostDevice, "Data DMA start: 0x%8x\n", SCSI_start);
1594             DPRINTF(UFSHostDevice, "Data DMA size: 0x%8x\n",
1595                     (sglist[count].size + 1));
1596             /**
1597              * safetynet; it has been shown that sg list may be optimistic in
1598              * the amount of data allocated, which can potentially lead to
1599              * some garbage data being send over. Hence this construction
1600              * that finds the least amount of data that needs to be
1601              * transfered.
1602              */
1603             uint32_t size_to_send = sglist[count].size + 1;
1604
1605             if (request_out_datain.msgSize < (size_to_send + size_accum))
1606                 size_to_send = request_out_datain.msgSize - size_accum;
1607
1608             readDevice(false, SCSI_start, size_to_send,
1609                        reinterpret_cast<uint8_t*>
1610                        (&(request_out_datain.message.dataMsg[size_accum])),
1611                        false, NULL);
1612
1613             size_accum += size_to_send;
1614             DPRINTF(UFSHostDevice, "Total remaining: 0x%8x,accumulated so far"
1615                     " : 0x%8x\n", (request_out_datain.msgSize - size_accum),
1616                     size_accum);
1617
1618             ++count;
1619             DPRINTF(UFSHostDevice, "Transfer #: %d\n", count);
1620         }
1621
1622         /**Go to the next stage of the answering process*/
1623         transferDone(response_addr, req_pos, UFSDevice[lun_id]->
1624                      transferInfo.requestOut, finalsize, finaladdress,
1625                      reinterpret_cast<uint8_t*>(request_in), true, lun_id);
1626     }
1627
1628     DPRINTF(UFSHostDevice, "SCSI resume done\n");
1629 }
1630
1631 /**
1632  * Find finished transfer. Callback function. One of the LUNs is done with
1633  * the disk transfer and reports back to the controller. This function finds
1634  * out who it was, and calls transferDone.
1635  */
1636 void
1637 UFSHostDevice::LUNSignal()
1638 {
1639     uint8_t this_lun = 0;
1640
1641     //while we haven't found the right lun, keep searching
1642     while ((this_lun < lunAvail) && !UFSDevice[this_lun]->finishedCommand())
1643         ++this_lun;
1644
1645     if (this_lun < lunAvail) {
1646         //Clear signal.
1647         UFSDevice[this_lun]->clearSignal();
1648         //found it; call transferDone
1649         transferDone(UFSDevice[this_lun]->transferInfo.responseStartAddr,
1650                      UFSDevice[this_lun]->transferInfo.reqPos,
1651                      UFSDevice[this_lun]->transferInfo.requestOut,
1652                      UFSDevice[this_lun]->transferInfo.size,
1653                      UFSDevice[this_lun]->transferInfo.address,
1654                      UFSDevice[this_lun]->transferInfo.destination,
1655                      UFSDevice[this_lun]->transferInfo.finished,
1656                      UFSDevice[this_lun]->transferInfo.lunID);
1657     }
1658
1659     else
1660         panic("no LUN finished in tick %d\n", curTick());
1661 }
1662
1663 /**
1664  * Transfer done. When the data transfer is done, this function ensures
1665  * that the application is notified.
1666  */
1667
1668 void
1669 UFSHostDevice::transferDone(Addr responseStartAddr, uint32_t req_pos,
1670                             struct UTPUPIURSP request_out, uint32_t size,
1671                             Addr address, uint8_t* destination,
1672                             bool finished, uint32_t lun_id)
1673 {
1674     /**Test whether SCSI queue hasn't popped prematurely*/
1675     if (UFSDevice[lun_id]->SCSIInfoQueue.empty())
1676         panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id,
1677               UFSHCIMem.TRUTRLDBR);
1678
1679     DPRINTF(UFSHostDevice, "DMA start: 0x%8x; DMA size: 0x%8x\n",
1680             responseStartAddr, sizeof(request_out));
1681
1682     struct transferStart lastinfo;
1683     lastinfo.mask = req_pos;
1684     lastinfo.done = finished;
1685     lastinfo.address = address;
1686     lastinfo.size = size;
1687     lastinfo.destination = reinterpret_cast<UTPTransferReqDesc*>
1688         (destination);
1689     lastinfo.lun_id = lun_id;
1690
1691     transferEnd.push_back(lastinfo);
1692
1693     DPRINTF(UFSHostDevice, "Transfer done start\n");
1694
1695     readDevice(false, responseStartAddr, sizeof(request_out),
1696                reinterpret_cast<uint8_t*>
1697                (&(UFSDevice[lun_id]->transferInfo.requestOut)),
1698                true, &UTPEvent);
1699 }
1700
1701 /**
1702  * finalUTP. Second part of the transfer done event.
1703  * this sends the final response: the UTP response. After this transaction
1704  * the doorbell shall be cleared, and the interupt shall be set.
1705  */
1706
1707 void
1708 UFSHostDevice::finalUTP()
1709 {
1710     uint32_t lun_id = transferEnd.front().lun_id;
1711
1712     UFSDevice[lun_id]->SCSIInfoQueue.pop_front();
1713     DPRINTF(UFSHostDevice, "SCSIInfoQueue size: %d, lun: %d\n",
1714             UFSDevice[lun_id]->SCSIInfoQueue.size(), lun_id);
1715
1716     /**stats**/
1717     if (UFSHCIMem.TRUTRLDBR & transferEnd.front().mask) {
1718         uint8_t count = 0;
1719         while (!(transferEnd.front().mask & (0x1 << count)))
1720             ++count;
1721         stats.transactionLatency.sample(curTick() -
1722                                         transactionStart[count]);
1723     }
1724
1725     /**Last message that will be transfered*/
1726     readDevice(true, transferEnd.front().address,
1727                transferEnd.front().size, reinterpret_cast<uint8_t*>
1728                (transferEnd.front().destination), true, NULL);
1729
1730     /**clean and ensure that the tracker is updated*/
1731     transferTrack &= ~(transferEnd.front().mask);
1732     --activeDoorbells;
1733     ++pendingDoorbells;
1734     garbage.push_back(transferEnd.front().destination);
1735     transferEnd.pop_front();
1736     DPRINTF(UFSHostDevice, "UTP handled\n");
1737
1738     /**stats**/
1739     stats.averageDoorbell = stats.maxDoorbell.value();
1740
1741     DPRINTF(UFSHostDevice, "activeDoorbells: %d, pendingDoorbells: %d,"
1742             " garbage: %d, TransferEvent: %d\n", activeDoorbells,
1743             pendingDoorbells, garbage.size(), transferEventQueue.size());
1744
1745     /**This is the moment that the device is available again*/
1746     if (!UFSDevice[lun_id]->SCSIInfoQueue.empty())
1747         SCSIResume(lun_id);
1748 }
1749
1750 /**
1751  * Read done handling function, is only initiated at the end of a transaction
1752  */
1753 void
1754 UFSHostDevice::readDone()
1755 {
1756     DPRINTF(UFSHostDevice, "Read done start\n");
1757     --readPendingNum;
1758
1759     /**Garbage collection; sort out the allocated UTP descriptor*/
1760     if (garbage.size() > 0) {
1761         delete garbage.front();
1762         garbage.pop_front();
1763         }
1764
1765     /**done, generate interrupt if we havent got one already*/
1766     if (!(UFSHCIMem.ORInterruptStatus & 0x01)) {
1767         UFSHCIMem.ORInterruptStatus |= UTPTransferREQCOMPL;
1768         generateInterrupt();
1769     }
1770
1771
1772     if (!readDoneEvent.empty()) {
1773         readDoneEvent.pop_front();
1774     }
1775 }
1776
1777 /**
1778  * set interrupt and sort out the doorbell register.
1779  */
1780
1781 void
1782 UFSHostDevice::generateInterrupt()
1783 {
1784     /**just to keep track of the transactions*/
1785     countInt++;
1786
1787     /**step5 clear doorbell*/
1788     UFSHCIMem.TRUTRLDBR &= transferTrack;
1789     pendingDoorbells = 0;
1790     DPRINTF(UFSHostDevice, "Clear doorbell %X\n", UFSHCIMem.TRUTRLDBR);
1791
1792     checkDrain();
1793
1794     /**step6 raise interrupt*/
1795     gic->sendInt(intNum);
1796     DPRINTF(UFSHostDevice, "Send interrupt @ transaction: 0x%8x!\n",
1797             countInt);
1798 }
1799
1800 /**
1801  * Clear interrupt
1802  */
1803
1804 void
1805 UFSHostDevice::clearInterrupt()
1806 {
1807     gic->clearInt(intNum);
1808     DPRINTF(UFSHostDevice, "Clear interrupt: 0x%8x!\n", countInt);
1809
1810     checkDrain();
1811
1812     if (!(UFSHCIMem.TRUTRLDBR)) {
1813         idlePhaseStart = curTick();
1814     }
1815     /**end of a transaction*/
1816 }
1817
1818 /**
1819  * Important to understand about the transfer flow:
1820  * We have basically three stages, The "system memory" stage, the "device
1821  * buffer" stage and the "disk" stage. In this model we assume an infinite
1822  * buffer, or a buffer that is big enough to store all the data in the
1823  * biggest transaction. Between the three stages are two queues. Those queues
1824  * store the messages to simulate their transaction from one stage to the
1825  * next. The manage{Action} function fills up one of the queues and triggers
1826  * the first event, which causes a chain reaction of events executed once
1827  * they pass through their queues. For a write action the stages are ordered
1828  * "system memory", "device buffer" and "disk", whereas the read transfers
1829  * happen "disk", "device buffer" and "system memory". The dma action in the
1830  * dma device is written from a bus perspective whereas this model is written
1831  * from a device perspective. To avoid confusion, the translation between the
1832  * two has been made in the writeDevice and readDevice funtions.
1833  */
1834
1835
1836 /**
1837  * Dma transaction function: write device. Note that the dma action is
1838  * from a device perspective, while this function is from an initiator
1839  * perspective
1840  */
1841
1842 void
1843 UFSHostDevice::writeDevice(Event* additional_action, bool toDisk, Addr
1844                            start, int size, uint8_t* destination, uint64_t
1845                            SCSIDiskOffset, uint32_t lun_id)
1846 {
1847     DPRINTF(UFSHostDevice, "Write transaction Start: 0x%8x; Size: %d\n",
1848             start, size);
1849
1850     /**check whether transfer is all the way to the flash*/
1851     if (toDisk) {
1852         ++writePendingNum;
1853
1854         while (!writeDoneEvent.empty() && (writeDoneEvent.front().when()
1855                                           < curTick()))
1856             writeDoneEvent.pop_front();
1857
1858         writeDoneEvent.push_back(
1859             EventFunctionWrapper([this]{ writeDone(); },
1860                                  name()));
1861         assert(!writeDoneEvent.back().scheduled());
1862
1863         /**destination is an offset here since we are writing to a disk*/
1864         struct transferInfo new_transfer;
1865         new_transfer.offset = SCSIDiskOffset;
1866         new_transfer.size = size;
1867         new_transfer.lunID = lun_id;
1868         new_transfer.filePointer = 0;
1869         SSDWriteinfo.push_back(new_transfer);
1870
1871         /**allocate appropriate buffer*/
1872         SSDWriteinfo.back().buffer.resize(size);
1873
1874         /**transaction*/
1875         dmaPort.dmaAction(MemCmd::ReadReq, start, size,
1876                           &writeDoneEvent.back(),
1877                           &SSDWriteinfo.back().buffer[0], 0);
1878         //yes, a readreq at a write device function is correct.
1879         DPRINTF(UFSHostDevice, "Write to disk scheduled\n");
1880
1881     } else {
1882         assert(!additional_action->scheduled());
1883         dmaPort.dmaAction(MemCmd::ReadReq, start, size,
1884                           additional_action, destination, 0);
1885         DPRINTF(UFSHostDevice, "Write scheduled\n");
1886     }
1887 }
1888
1889 /**
1890  * Manage write transfer. Manages correct transfer flow and makes sure that
1891  * the queues are filled on time
1892  */
1893
1894 void
1895 UFSHostDevice::manageWriteTransfer(uint8_t LUN, uint64_t offset, uint32_t
1896                                    sg_table_length, struct UFSHCDSGEntry*
1897                                    sglist)
1898 {
1899     struct writeToDiskBurst next_packet;
1900
1901     next_packet.SCSIDiskOffset = offset;
1902
1903     UFSDevice[LUN]->setTotalWrite(sg_table_length);
1904
1905     /**
1906      * Break-up the transactions into actions defined by the scatter gather
1907      * list.
1908      */
1909     for (uint32_t count = 0; count < sg_table_length; count++) {
1910         next_packet.start = sglist[count].upperAddr;
1911         next_packet.start = (next_packet.start << 32) |
1912             (sglist[count].baseAddr & 0xFFFFFFFF);
1913         next_packet.LUN = LUN;
1914         DPRINTF(UFSHostDevice, "Write data DMA start: 0x%8x\n",
1915                 next_packet.start);
1916         DPRINTF(UFSHostDevice, "Write data DMA size: 0x%8x\n",
1917                 (sglist[count].size + 1));
1918         assert(sglist[count].size > 0);
1919
1920         if (count != 0)
1921             next_packet.SCSIDiskOffset = next_packet.SCSIDiskOffset +
1922                 (sglist[count - 1].size + 1);
1923
1924         next_packet.size = sglist[count].size + 1;
1925
1926         /**If the queue is empty, the transaction should be initiated*/
1927         if (dmaWriteInfo.empty())
1928             writeDevice(NULL, true, next_packet.start, next_packet.size,
1929                         NULL, next_packet.SCSIDiskOffset, next_packet.LUN);
1930         else
1931             DPRINTF(UFSHostDevice, "Write not initiated queue: %d\n",
1932                     dmaWriteInfo.size());
1933
1934         dmaWriteInfo.push_back(next_packet);
1935         DPRINTF(UFSHostDevice, "Write Location: 0x%8x\n",
1936                 next_packet.SCSIDiskOffset);
1937
1938         DPRINTF(UFSHostDevice, "Write transfer #: 0x%8x\n", count + 1);
1939
1940         /** stats **/
1941         stats.totalWrittenSSD += (sglist[count].size + 1);
1942     }
1943
1944     /**stats**/
1945     ++stats.totalWriteUFSTransactions;
1946 }
1947
1948 /**
1949  * Write done handling function. Is only initiated when the flash is directly
1950  * approached
1951  */
1952
1953 void
1954 UFSHostDevice::writeDone()
1955 {
1956     /**DMA is done, information no longer needed*/
1957     assert(dmaWriteInfo.size() > 0);
1958     dmaWriteInfo.pop_front();
1959     assert(SSDWriteinfo.size() > 0);
1960     uint32_t lun = SSDWriteinfo.front().lunID;
1961
1962     /**If there is nothing on the way, we need to start the events*/
1963     DPRINTF(UFSHostDevice, "Write done entered, queue: %d\n",
1964             UFSDevice[lun]->SSDWriteDoneInfo.size());
1965     /**Write the disk*/
1966     UFSDevice[lun]->writeFlash(&SSDWriteinfo.front().buffer[0],
1967                                SSDWriteinfo.front().offset,
1968                                SSDWriteinfo.front().size);
1969
1970     /**
1971      * Move to the second queue, enter the logic unit
1972      * This is where the disk is approached and the flash transaction is
1973      * handled SSDWriteDone will take care of the timing
1974      */
1975     UFSDevice[lun]->SSDWriteDoneInfo.push_back(SSDWriteinfo.front());
1976     SSDWriteinfo.pop_front();
1977
1978     --writePendingNum;
1979     /**so far, only the DMA part has been handled, lets do the disk delay*/
1980     UFSDevice[lun]->SSDWriteStart();
1981
1982     /** stats **/
1983     stats.currentWriteSSDQueue = UFSDevice[lun]->SSDWriteDoneInfo.size();
1984     stats.averageWriteSSDQueue = UFSDevice[lun]->SSDWriteDoneInfo.size();
1985     ++stats.totalWriteDiskTransactions;
1986
1987     /**initiate the next dma action (if any)*/
1988     if (!dmaWriteInfo.empty())
1989         writeDevice(NULL, true, dmaWriteInfo.front().start,
1990                     dmaWriteInfo.front().size,  NULL,
1991                     dmaWriteInfo.front().SCSIDiskOffset,
1992                     dmaWriteInfo.front().LUN);
1993     DPRINTF(UFSHostDevice, "Write done end\n");
1994 }
1995
1996 /**
1997  * SSD write start. Starts the write action in the timing model
1998  */
1999 void
2000 UFSHostDevice::UFSSCSIDevice::SSDWriteStart()
2001 {
2002     assert(SSDWriteDoneInfo.size() > 0);
2003     flashDevice->writeMemory(
2004         SSDWriteDoneInfo.front().offset,
2005         SSDWriteDoneInfo.front().size, memWriteCallback);
2006
2007     SSDWriteDoneInfo.pop_front();
2008
2009     DPRINTF(UFSHostDevice, "Write is started; left in queue: %d\n",
2010             SSDWriteDoneInfo.size());
2011 }
2012
2013
2014 /**
2015  * SSDisk write done
2016  */
2017
2018 void
2019 UFSHostDevice::UFSSCSIDevice::SSDWriteDone()
2020 {
2021     DPRINTF(UFSHostDevice, "Write disk, aiming for %d messages, %d so far\n",
2022             totalWrite, amountOfWriteTransfers);
2023
2024     //we have done one extra transfer
2025     ++amountOfWriteTransfers;
2026
2027     /**test whether call was correct*/
2028     assert(totalWrite >= amountOfWriteTransfers && totalWrite != 0);
2029
2030     /**are we there yet? (did we do everything)*/
2031     if (totalWrite == amountOfWriteTransfers) {
2032         DPRINTF(UFSHostDevice, "Write transactions finished\n");
2033         totalWrite = 0;
2034         amountOfWriteTransfers = 0;
2035
2036         //Callback UFS Host
2037         setSignal();
2038         signalDone();
2039     }
2040
2041 }
2042
2043 /**
2044  * Dma transaction function: read device. Notice that the dma action is from
2045  * a device perspective, while this function is from an initiator perspective
2046  */
2047
2048 void
2049 UFSHostDevice::readDevice(bool lastTransfer, Addr start, uint32_t size,
2050                           uint8_t* destination, bool no_cache, Event*
2051                           additional_action)
2052 {
2053     DPRINTF(UFSHostDevice, "Read start: 0x%8x; Size: %d, data[0]: 0x%8x\n",
2054             start, size, (reinterpret_cast<uint32_t *>(destination))[0]);
2055
2056     /** check wether interrupt is needed */
2057     if (lastTransfer) {
2058         ++readPendingNum;
2059         readDoneEvent.push_back(
2060             EventFunctionWrapper([this]{ readDone(); },
2061                                  name()));
2062         assert(!readDoneEvent.back().scheduled());
2063         dmaPort.dmaAction(MemCmd::WriteReq, start, size,
2064                           &readDoneEvent.back(), destination, 0);
2065         //yes, a writereq at a read device function is correct.
2066
2067     } else {
2068         if (additional_action != NULL)
2069             assert(!additional_action->scheduled());
2070
2071         dmaPort.dmaAction(MemCmd::WriteReq, start, size,
2072                           additional_action, destination, 0);
2073
2074     }
2075
2076 }
2077
2078 /**
2079  * Manage read transfer. Manages correct transfer flow and makes sure that
2080  * the queues are filled on time
2081  */
2082
2083 void
2084 UFSHostDevice::manageReadTransfer(uint32_t size, uint32_t LUN, uint64_t
2085                                   offset, uint32_t sg_table_length,
2086                                   struct UFSHCDSGEntry* sglist)
2087 {
2088     uint32_t size_accum = 0;
2089
2090     DPRINTF(UFSHostDevice, "Data READ size: %d\n", size);
2091
2092     /**
2093      * Break-up the transactions into actions defined by the scatter gather
2094      * list.
2095      */
2096     for (uint32_t count = 0; count < sg_table_length; count++) {
2097         struct transferInfo new_transfer;
2098         new_transfer.offset = sglist[count].upperAddr;
2099         new_transfer.offset = (new_transfer.offset << 32) |
2100             (sglist[count].baseAddr & 0xFFFFFFFF);
2101         new_transfer.filePointer = offset + size_accum;
2102         new_transfer.size = (sglist[count].size + 1);
2103         new_transfer.lunID = LUN;
2104
2105         DPRINTF(UFSHostDevice, "Data READ start: 0x%8x; size: %d\n",
2106                 new_transfer.offset, new_transfer.size);
2107
2108         UFSDevice[LUN]->SSDReadInfo.push_back(new_transfer);
2109         UFSDevice[LUN]->SSDReadInfo.back().buffer.resize(sglist[count].size
2110                                                          + 1);
2111
2112         /**
2113          * The disk image is read here; but the action is simultated later
2114          * You can see this as the preparation stage, whereas later is the
2115          * simulation phase.
2116          */
2117         UFSDevice[LUN]->readFlash(&UFSDevice[LUN]->
2118                                   SSDReadInfo.back().buffer[0],
2119                                   offset + size_accum,
2120                                   sglist[count].size + 1);
2121
2122         size_accum += (sglist[count].size + 1);
2123
2124         DPRINTF(UFSHostDevice, "Transfer %d; Remaining: 0x%8x, Accumulated:"
2125                 " 0x%8x\n", (count + 1), (size-size_accum), size_accum);
2126
2127         /** stats **/
2128         stats.totalReadSSD += (sglist[count].size + 1);
2129         stats.currentReadSSDQueue = UFSDevice[LUN]->SSDReadInfo.size();
2130         stats.averageReadSSDQueue = UFSDevice[LUN]->SSDReadInfo.size();
2131     }
2132
2133     UFSDevice[LUN]->SSDReadStart(sg_table_length);
2134
2135     /** stats **/
2136     ++stats.totalReadUFSTransactions;
2137
2138 }
2139
2140
2141
2142 /**
2143  * SSDisk start read; this function was created to keep the interfaces
2144  * between the layers simpler. Without this function UFSHost would need to
2145  * know about the flashdevice.
2146  */
2147
2148 void
2149 UFSHostDevice::UFSSCSIDevice::SSDReadStart(uint32_t total_read)
2150 {
2151     totalRead = total_read;
2152     for (uint32_t number_handled = 0; number_handled < SSDReadInfo.size();
2153          number_handled++) {
2154         /**
2155          * Load all the read request to the Memory device.
2156          * It will call back when done.
2157          */
2158         flashDevice->readMemory(SSDReadInfo.front().filePointer,
2159                                 SSDReadInfo.front().size, memReadCallback);
2160     }
2161
2162 }
2163
2164
2165 /**
2166  * SSDisk read done
2167  */
2168
2169 void
2170 UFSHostDevice::UFSSCSIDevice::SSDReadDone()
2171 {
2172     DPRINTF(UFSHostDevice, "SSD read done at lun %d, Aiming for %d messages,"
2173             " %d so far\n", lunID, totalRead, amountOfReadTransfers);
2174
2175     if (totalRead == amountOfReadTransfers) {
2176         totalRead = 0;
2177         amountOfReadTransfers = 0;
2178
2179         /**Callback: transferdone*/
2180         setSignal();
2181         signalDone();
2182     }
2183
2184 }
2185
2186 /**
2187  * Read callback, on the way from the disk to the DMA. Called by the flash
2188  * layer. Intermediate step to the host layer
2189  */
2190 void
2191 UFSHostDevice::UFSSCSIDevice::readCallback()
2192 {
2193     ++amountOfReadTransfers;
2194
2195     /**Callback; make sure data is transfered upstream:
2196      * UFSHostDevice::readCallback
2197      */
2198     setReadSignal();
2199     deviceReadCallback();
2200
2201     //Are we done yet?
2202     SSDReadDone();
2203 }
2204
2205 /**
2206  * Read callback, on the way from the disk to the DMA. Called by the UFSSCSI
2207  * layer.
2208  */
2209
2210 void
2211 UFSHostDevice::readCallback()
2212 {
2213     DPRINTF(UFSHostDevice, "Read Callback\n");
2214     uint8_t this_lun = 0;
2215
2216     //while we haven't found the right lun, keep searching
2217     while ((this_lun < lunAvail) && !UFSDevice[this_lun]->finishedRead())
2218         ++this_lun;
2219
2220     DPRINTF(UFSHostDevice, "Found LUN %d messages pending for clean: %d\n",
2221             this_lun, SSDReadPending.size());
2222
2223     if (this_lun < lunAvail) {
2224         //Clear signal.
2225         UFSDevice[this_lun]->clearReadSignal();
2226         SSDReadPending.push_back(UFSDevice[this_lun]->SSDReadInfo.front());
2227         UFSDevice[this_lun]->SSDReadInfo.pop_front();
2228         readGarbageEventQueue.push_back(
2229             EventFunctionWrapper([this]{ readGarbage(); }, name()));
2230
2231         //make sure the queue is popped a the end of the dma transaction
2232         readDevice(false, SSDReadPending.front().offset,
2233                    SSDReadPending.front().size,
2234                    &SSDReadPending.front().buffer[0], false,
2235                    &readGarbageEventQueue.back());
2236
2237         /**stats*/
2238         ++stats.totalReadDiskTransactions;
2239     }
2240     else
2241         panic("no read finished in tick %d\n", curTick());
2242 }
2243
2244 /**
2245  * After a disk read DMA transfer, the structure needs to be freed. This is
2246  * done in this function.
2247  */
2248 void
2249 UFSHostDevice::readGarbage()
2250 {
2251     DPRINTF(UFSHostDevice, "Clean read data, %d\n", SSDReadPending.size());
2252     SSDReadPending.pop_front();
2253     readGarbageEventQueue.pop_front();
2254 }
2255
2256 /**
2257  * Serialize; needed to make checkpoints
2258  */
2259
2260 void
2261 UFSHostDevice::serialize(CheckpointOut &cp) const
2262 {
2263     DmaDevice::serialize(cp);
2264
2265     const uint8_t* temp_HCI_mem = reinterpret_cast<const uint8_t*>(&UFSHCIMem);
2266     SERIALIZE_ARRAY(temp_HCI_mem, sizeof(HCIMem));
2267
2268     uint32_t lun_avail = lunAvail;
2269     SERIALIZE_SCALAR(lun_avail);
2270 }
2271
2272
2273 /**
2274  * Unserialize; needed to restore from checkpoints
2275  */
2276
2277 void
2278 UFSHostDevice::unserialize(CheckpointIn &cp)
2279 {
2280     DmaDevice::unserialize(cp);
2281     uint8_t* temp_HCI_mem = reinterpret_cast<uint8_t*>(&UFSHCIMem);
2282     UNSERIALIZE_ARRAY(temp_HCI_mem, sizeof(HCIMem));
2283
2284     uint32_t lun_avail;
2285     UNSERIALIZE_SCALAR(lun_avail);
2286     assert(lunAvail == lun_avail);
2287 }
2288
2289
2290 /**
2291  * Drain; needed to enable checkpoints
2292  */
2293
2294 DrainState
2295 UFSHostDevice::drain()
2296 {
2297     if (UFSHCIMem.TRUTRLDBR) {
2298         DPRINTF(UFSHostDevice, "UFSDevice is draining...\n");
2299         return DrainState::Draining;
2300     } else {
2301         DPRINTF(UFSHostDevice, "UFSDevice drained\n");
2302         return DrainState::Drained;
2303     }
2304 }
2305
2306 /**
2307  * Checkdrain; needed to enable checkpoints
2308  */
2309
2310 void
2311 UFSHostDevice::checkDrain()
2312 {
2313     if (drainState() != DrainState::Draining)
2314         return;
2315
2316     if (UFSHCIMem.TRUTRLDBR) {
2317         DPRINTF(UFSHostDevice, "UFSDevice is still draining; with %d active"
2318             " doorbells\n", activeDoorbells);
2319     } else {
2320         DPRINTF(UFSHostDevice, "UFSDevice is done draining\n");
2321         signalDrainDone();
2322     }
2323 }